NEC 78K0/KD1 Series User Manual page 314

(2) Serial clock selection register 10 (CSIC10)
CSIC10 is used to select the phase of the data clock and set the count clock.
CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 15-3. Format of Serial Clock Selection Register 10 (CSIC10)
Address: FF81H After reset: 00H R/W
Symbol 7
CSIC10 0
CKP10
0
0
1
1
CKS102
0
0
0
0
1
1
1
1
Cautions 1. Do not write CSIC10 during a communication operation or when using P10/SCK10/T
P11/SI10/R
2. The phase type of the data clock is type 1 after reset.
Remarks 1. Figures in parentheses are for operation with f
2. f : X1 input clock oscillation frequency
X
314
CHAPTER 15 SERIAL INTERFACE CSI10
6 5
0 0 CKP10
DAP10
0
SCK10
SO10
SI10 input timing
1
SCK10
SO10
SI10 input timing
0
SCK10
SO10
SI10 input timing
1
SCK10
SO10
SI10 input timing
CKS101 CKS100
0 0 f /2 (5 MHz)
X
0 1 f /2
X
1 0 f /2
X
1 1 f /2
X
0 0 f /2
X
0 1 f /2
X
1 0 f /2
X
1 1 External clock input to SCK10
D0, and P12/SO10 as general-purpose port pins.
X
Preliminary User's Manual U16315EJ1V0UD
4 3
DAP10 CKS102
Data clock phase selection
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSI10 count clock selection
2
(2.5 MHz)
3
(1.25 MHz)
4
(625 kHz)
5
(312.5 kHz)
6
(156.25 kHz)
7
(78.13 kHz)
= 10 MHz
X
2 1 0
CKS101 CKS100
Type
1
2
3
4
D0,
X