NEC 78K0/KD1 Series User Manual page 132

CR000 can be set by a 16-bit memory manipulation instruction.
RESET input clears CR000 to 0000H.
Cautions 1. Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a match
of TM00 and CR000. However, in the free-running mode and in the clear mode using the
valid edge of TI000, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated
following overflow (FFFFH).
2. If the changed value of CR000 is smaller than the value of 16-bit timer counter 00 (TM00),
TM00 continues counting and starts counting again from 0 after overflow. Therefore, if the
value of CR000 after the change is smaller than before the change, the timer should be
restarted after CR000 is changed.
3. When P01 is used as the valid edge of TI010, it cannot be used as the timer output (TO00).
Moreover, when P01 is used as TO00, it cannot be used as the valid edge of TI010.
4. When CR000 is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
5. Do not rewrite CR000 during TM00 operation.
(3) 16-bit timer capture/compare register 010 (CR010)
CR010 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00
(CRC00).
• • • • When CR010 is used as a compare register
The value set in the CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and
an interrupt request (INTTM010) is generated if they match.
• • • • When CR010 is used as a capture register
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by
prescaler mode register 00 (PRM00).
CR010 can be set by a 16-bit memory manipulation instruction.
RESET input clears CR010 to 0000H.
Cautions 1. Set CR010 to other than 0000H. This means a 1-pulse count operation cannot be performed
when CR010 is used as the event counter.
However, in the free-running mode and in the clear mode using the valid edge of TI000, if
CR010 is set to 0000H, an interrupt request (INTTM010) is generated following overflow
(FFFFH).
2. When CR010 is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
3. CR010 can be rewritten during TM00 operation. For details, refer to Remark 2 in Figure 6-12.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User's Manual U16315EJ1V0UD