Cautions For 8-Bit Timer/Event Counters 50 And 51 - NEC 78K0/KD1 Series User Manual

(2) Operation with CR5n changed
(a) CR5n value is changed from N to M before clock rising edge of FFH
Count clock
TM5n N N + 1 N + 2
CR5n N
TCE5n
H
INTTM5n
TO5n
<1> CR5n change (N → M)
(b) CR5n value is changed from N to M after clock rising edge of FFH
→ Value is reloaded to CR5n at second overflow.
Count clock
TM5n N N + 1 N + 2
CR5n N
TCE5n
H
INTTM5n
TO5n
<1> CR5n change (N → M)
Caution When reading from CR5n between <1> and <2> in Figure 7-13, the value read differs from the
actual value (read value: M, actual value of CR5n: N).

7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51

(1) Timer start error
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.
TM5n count value
Remark n = 0, 1
178
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Figure 7-13. Timing of Operation with CR5n Changed
→ → → → Value is reloaded to CR5n at overflow immediately after change.
FFH 00H 01H 02H
M
<2>
FFH 00H 01H 02H
N
Figure 7-14. 8-Bit Timer Counter 5n Start Timing
Count clock
00H
Timer start
Preliminary User's Manual U16315EJ1V0UD
M M + 1 M + 2 FFH 00H 01H 02H
N N + 1 N + 2 FFH 00H 01H 02H
<2>
01H 02H 03H
M M + 1 M + 2
M M + 1 M + 2
M
04H