NEC 78K0/KD1 Series User Manual page 244

8-bit single-chip microcontrollers
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(11) A/D converter sampling time and A/D conversion start delay time
The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM).
The delay time exists until actual sampling is started after A/D converter operation is enabled.
When using a set in which the A/D conversion time must be strictly observed, care is required for the contents
shown in Figure 12-23 and Table 12-3.
Figure 12-23. Timing of A/D Converter Sampling and A/D Conversion Start Delay
ADCS ← 1 or ADS rewrite
ADCS
Sampling timing
INTAD
Table 12-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value)
FR2
FR1
FR0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
Other than above
Note The A/D conversion start delay time is the time after wait period. For the wait function, refer to CHAPTER 29
CAUTIONS FOR WAIT.
Remark f
: X1 clock oscillation frequency
X
244
CHAPTER 12 A/D CONVERTER
Wait
A/D
Sampling
period
conversion
time
start delay
time
Conversion Time
288/f
X
240/f
X
192/f
X
144/f
X
120/f
X
96/f
X
Setting prohibited
Preliminary User's Manual U16315EJ1V0UD
Conversion time
Sampling Time
A/D Conversion Start Delay Time
MIN.
40/f
32/f
X
X
32/f
28/f
X
X
24/f
24/f
X
X
20/f
16/f
X
X
16/f
14/f
X
X
12/f
12/f
X
X
Note
MAX.
36/f
X
32/f
X
28/f
X
18/f
X
16/f
X
14/f
X

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