Stop Mode - NEC 78K0/KD1 Series User Manual

18.2.2 STOP mode

(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the X1 input clock or Ring-OSC clock.
Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is
immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after
execution of the STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has elapsed.
The operating statuses in the STOP mode are shown below.
STOP Mode Setting
Item
System clock
CPU
Port (latch)
16-bit timer/event counter 00
8-bit timer/event counter 50
8-bit timer/event counter 51
8-bit timer H0
8-bit timer H1
Watch timer
Watchdog Ring-OSC cannot
Note 4
timer be stopped
Ring-OSC can be
Note 4
stopped
A/D converter
Serial interface UART0
UART6
CSI10
Clock monitor
Note 5
Power-on-clear function
Low-voltage detection function
External interrupt
Notes 1. When "Stopped by software" is selected for Ring-OSC by a mask option and Ring-OSC is stopped by
software (for mask options, see CHAPTER 24 MASK OPTIONS).
2. Operation continues only when f
3. Operable when the subsystem clock is selected.
4. "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software" can be selected by a mask
option.
5. When "POC used" is selected by a mask option.
CHAPTER 18 STANDBY FUNCTION
Table 18-4. Operating Statuses in STOP Mode
When STOP Instruction Is Executed While CPU Is Operating on X1 Input Clock
When Ring-OSC Oscillation
Continues
When Subsystem When Subsystem
Clock Used Clock Not Used
Only X1 oscillator oscillation is stopped. Clock supply to the CPU is stopped.
Operation stopped
Status before STOP mode was set is retained
Operation stopped
Operable only when TI50 is selected as the count clock
Operable only when TI51 is selected as the count clock
Operable only when TO50 is selected as the count clock during 8-bit timer/event counter 50 operation
Note 2
Operable
Note 3
Operable Operation stopped Operable
Operable
Operation stopped
Operation stopped
Operable only when TO50 is selected as the serial clock during TM50 operation
Operable only when external SCK10 is selected as the serial clock
Operation stopped
Operable
Operable
Operable
7
/2 is selected as the count clock.
R
Preliminary User's Manual U16315EJ1V0UD
When Ring-OSC Oscillation
Note 1
Stopped
When Subsystem When Subsystem
Clock Used Clock Not Used
Operation stopped
Note 3
Operation stopped Operable
−
When STOP Instruction Is Executed
While CPU Is Operating on Ring-
OSC Clock
When Subsystem When Subsystem
Clock Used Clock Not Used
Note 2
Operable
Note 3
Operation stopped
Operable
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