NEC 78K0/KD1 Series User Manual page 159

(4) Capture register data retention timing
If the valid edge of the TI000 pin is input during 16-bit timer capture/compare register 010 (CR010) read, CR010
performs a capture operation. However, the value read at this time is not guaranteed.
The interrupt request flag (TMIF010) is set upon detection of the valid edge.
Count clock
TM00 count value
Edge input
Interrupt request flag
Capture read signal
CR010 interrupt value
(5) Valid edge setting
Set the valid edge of the TI000 pin after setting bits 2 and 3 (TMC002 and TMC003) of 16-bit timer mode control
register 00 (TMC00) to 0, 0, respectively, and then stopping timer operation. The valid edge is set using bits 4
and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00).
(6) Re-triggering one-shot pulse
(a) One-shot pulse output by software
When a one-shot pulse is output, do not set the OSPT00 bit to 1. Do not output the one-shot pulse again
until INTTM000, which occurs upon a match with the CR000 register, or INTTM010, which occurs upon a
match with the CR010 register, occurs.
(b) One-shot pulse output with external trigger
If the external trigger occurs again while a one-shot pulse is output, it is ignored.
(c) One-shot pulse output function
When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change
the level of the TI000 pin or its alternate function port pin.
Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the
TI000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-34. Capture Register Data Retention Timing
N N + 1
X
Preliminary User's Manual U16315EJ1V0UD
N + 2 M
N + 2
Capture
M + 1 M + 2
M + 1
Capture, but
read value is
not guaranteed
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