Hop Time Example - Analog Devices ADRV9001 User Manual

Preliminary Technical Data

HOP TIME EXAMPLE

1. This example shows a frequency diagram for a 2-LO case for the Fast frequency hopping mode. The hop is occurring on Tx and Rx
frames. We will demonstrate how ARM and stream processor will operate in each time. In this example, there is a one-frame delay
between the HOP signal and the frame on the air. There are two sets of registers A and B for the algorithm coefficients. These
register sets work similarly as RF LO1 and RF LO2 so that one can be used while the other one is being prepared.
2. First, the Rx setup is sent from BBIC to indicate to ARM that the upcoming frame (frame #0) will be operating on Rx. At this point,
the frequency information has been indicated by the BBIC through API. ARM gets this frequency information (F1) and prepares
DMA to update RF LO1 to F1. ARM also prepares algorithm coefficients generated in initialization time for frequency F1. At this
point, the coefficients are not applied, they are simply being prepared. Streams take no action.
3. Next, at the first rising edge of the HOP signal, the main stream processor triggers DMA to tune RF LO1 to F1. ARM is interrupted
by the stream and prepares the DMA to power up RF LO1 for the next frame. ARM writes Rx algorithm coefficients to, in this case,
B registers for the next hop frame.
4. At the falling edge of the Rx setup signal, the main stream processor takes no action, ARM takes no action, Rx stream processor
reads the upcoming frame is Rx and starts to power up the digital and analog components for Rx.
5. The rising edge of the Tx setup signal indicates the upcoming frame (frame #1) will operate on Tx. ARM gets the next frequency and
gain information (F2) and prepares DMA to update RF LO2 to F2. ARM prepares algorithm coefficients for frequency F2. Streams
take no action.
6. At HOP signal falling edge, the main stream processor triggers DMA to tune RF LO2 to F2. DMA powers up the RF LO1. It also
toggles the HOP register to switch to B registers. ARM is interrupted by the stream to update DMA so that RF LO2 is powered up
next frame and LO1 is powered down. RX stream processor reads that RX is active in this frame. The falling edge of Rx has already
powered up the digital and analog components. At this point, the stream processor just powers up the Rx LO mux buffer and
unmasks the ADC output. ARM writes Tx algorithm coefficients to the next A registers for the next hop frame (frame #1).
7. At the falling edge of the Tx setup signal, the main stream processor takes no action. ARM takes no action. Tx stream processor
reads that the next frame is Tx and starts powering up digital and analog components.
8. Finally, at the next rising edge of the HOP signal (start of frame#2), the main stream processor triggers DMA to power down RF
LO1, tune RF LO1 to F3, and DMA to power up the RF LO2. ARM is interrupted by stream to update DMA so that LO1 is powered
up next frame and LO2 is powered down. Tx stream processor reads that Tx is active in this frame. The falling edge of the Tx setup
has already powered up the digital and analog components. At this point, the stream processor just powers up the Tx LO mux buffer
and unmasks the DAC output. ARM saves updated Rx algorithm coefficients from previous B registers (for just completed hop
frame, frame #0). ARM writes Rx algorithm coefficients to the next B registers for the next hop frame (frame #2).
0 1
HOP
Rx SETUP
Tx SETUP
FREQUENCY F1 F2 F3
SELECT (MSG)
RETUNE PLL
PLL READY
FRAME NO 0
CHANNEL – – RX
FREQUENCY – – F1
LO – – LO1
Figure 84. Frequency Hopping (Fast Frequency Hopping Mode) Timing Diagram
Rev. PrA | Page 89 of 253
2 3 4 5 6
F4 F1 F2 F3 F4
1 2 3 4 5
TX RX TX RX TX
F2 F3 F4 F1 F2
LO2 LO1 LO2 LO1 LO2 LO1
7
BBIC
BBIC
BBIC
BBIC
6 7
RX TX
F3 F4
LO2
UG-1828