Analog Devices ADRV9001 User Manual page 56

UG-1828
An additional port might be used as a reference clock for the baseband processor to generate above Transmit LSSI clock, Strobe and Data
signal, the user could use RX1_DCLK_OUT or RX2_DCLK_OUT as a reference clock if these clock frequencies are equal to the TX clock
frequency.
An optional LVDS port (alternative function of Digital GPIO) can also be configured as an output LVDS pad used as a reference clock
TX_DCLK_OUT (±) for the baseband processor, the user could use TX_DCLK_OUT to generate above LSSI clock, strobe and data
signal.
Transmit LSSI Interface with Separate Lanes for I and Q
Figure 47 illustrates the transmit LSSI interface (Tx1 and Tx2) for a 16-bit I/Q data sample with MSB first configuration.
TX_DCLK_OUT+
TX_DCLK_IN+
TX_DCLK_IN+
TX_STROBE_IN+
TX_STROBE_IN+
TX_IDATA_IN+/–
TX_QDATA_IN+/–
Figure 48 illustrates the Transmit LSSI interface (Tx1 and Tx2) for a 12-bit I/Q data sample with MSB first configuration.
TX_DCLK_OUT+
TX_DCLK_IN+
TX_DCLK_IN+
TX_STROBE_IN+
TX_STROBE_IN+
TX_IDATA_IN+/–
TX_QDATA_IN+/–
The TX_STROBE signal is aligned with the first bit of the serialized data (I & Q), and can be configured to be high:
For a half clock cycle at start of I and Q sample transmit. In the case a 16-bit data sample, the TX_STROBE is high for a half clock
•
cycle and low for a half and 15 clock cycles. In the case of a 12-bit data sample, the TX_STROBE is high for a half clock cycle and
low for a half and 11 clock cycles.
For half of I and Q data duration. In the case of a 16-bit data sample, the TX_STROBE is high for 4 clock cycles, and low for 4 clock
•
cycles (Q data sample). In the case of a 12-bit data sample, the TX_STROBE is high for 3 clock cycles and low for 3 clock cycles.
In 12-bit I/Q mode, 12-bit samples from LSSI are extended to 16 bits by padding four bits zero in LSB for the following transmit datapath
process.
OR
OR
I0_D15
Q0_D15
Figure 47. Transmit LSSI Timing for 16-Bit I/Q Data Sample on Separate Lanes
OR
OR
I0_D11
Q0_D11
Figure 48. Transmit LSSI Timing for 12-Bit I/Q Data Sample on Separate Lanes
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I0_D8 I0_D7 I0_D0
Q0_D8 Q0_D7 Q0_D0
I0_D6 I0_D5 I0_D0
Q0_D6 Q0_D5 Q0_D0
Preliminary Technical Data
I1_D15 I1_D14
Q1_D15 Q1_D14
I1_D11 I1_D10
Q1_D11 Q1_D10