General Transmitter Bias And Port Interface - Analog Devices ADRV9001 User Manual

Preliminary Technical Data
Example of RX1 A Port Frequency Match Simulation
Reasonable approximation of return loss of a frequency matching network can be obtained with a simple S parameter simulation
available in ADS without PCB artwork. Figure 165 illustrates a wide-band frequency match simulation setup in ADS for ADRV9001
RX1(2) A input pins in ADS for evaluating a possible configuration for a desired match to 3 GHz.
0 0.5
S parameters for a selected balun and ac-coupling SMD type caps and ADRV9001 RX input impedance can be used to represent balun's
balanced side interface to the device. Shunt and series matching component can be added with short TLs to represent possible PCB traces
associated with these matching components on the single side of balun. Peaking of return loss at 2.5 GHz looking into the single-ended
interface of balun has been reduced by a clockwise rotation of high frequency portion of S11 curve on the Smith chart by adding a shunt
capacitor followed by series inductor after short transmission lines away from the balun's single-ended terminal.

GENERAL TRANSMITTER BIAS AND PORT INTERFACE

This section considers the dc biasing of the ADRV9001 transmitter (Tx) outputs and how to interface to each Tx port. ADRV9001
transmitters operate over a range of frequencies. At full output power, each differential output side draws approximately 100mA of DC
bias current. The Tx outputs are DC biased to a 1.8V supply voltage using either RF chokes (wire-wound inductors) or a transformer
center tap connection.
Careful design of the DC bias network is required to ensure optimal RF performance levels. When designing the DC bias network, select
components with low DC resistance (R
Figure 165. ADS Simulation Example Setup with Simple Physical Board Trace Models
1.0 1.5 2.0 2.5
FREQUENCY (GHz)
AT THE FINAL SERIES INDUCTOR WITH A SHORT TL
AT THE SINGLE-ENDED TERMINAL OF BALUN
AT THE FIRST SHUNT CAPACITOR WITH A SHORT TL
Figure 166. ADS Simulation Results of Return Loss Curve
) to minimize the voltage drop across the series parasitic resistance element with either of the
DCR
Rev. PrA | Page 189 of 253
3.0
FREQUENCY (10MHZ TO 3GHZ)
UG-1828
H