Cssi/Lssi Testability And Debug - Analog Devices ADRV9001 User Manual

UG-1828
Table 18. LVDS SSI Timing Specification
LVDS SSI
Rx t (Maximum)
DELAY
Tx t (Minimum)
SETUP
Tx t (Minimum)
HOLD

CSSI/LSSI TESTABILITY AND DEBUG

ADRV9001 SSI has built-in test pattern generator and test pattern checker which can help users to quickly test and debug the SSI
interface between the ADRV9001 and the baseband processor. Figure 52 illustrates the ADRV9001 SSI testability and debug diagram
with a baseband processor.
DAC
DATA PATH
DAC
DATA PATH
ADC
DATA PATH
ADC
DATA PATH
ADRV9001 receive SSI can generate ramp or PRBS (LSSI only) pattern and replace the receive channel data to baseband processor when
enable the receive debug function, users can check the specified test pattern at their SSI output to test if the receive SSI works well.
ADRV9001 transmit SSI has ramp and PRBS (LSSI only) pattern checker, users can transmit ramp or PRBS pattern rather than user
transmit data via SSI to ADRV9001 to verify if transmit SSI works well. Moreover, ADRV9001 transmit SSI always monitors the
TX_STROBE_IN signal validity according the SSI work modes and reports the error flag if finds the strobe misalignment.
ADRV9001 transmit SSI data output can be loopback to receive SSI data input when transmit and receive SSI runs at same clock rate,
users can utilize themselves pattern generator and checker to verify if the whole system SSI works well.
As mentioned earier, the SSI clock, strobe and data have programable delay, this helps users to meet the timing spec that described in SSI
Timing Parameters.
Timing
200 ps
200 ps
300 ps
TX1
TX2
RX1
RX2
Figure 52. ADRV9001 SSI Testability and Debug Diagram
Description
Clock to strobe/data delay
Strobe/data setup to clock
Strobe/data hold after clock
DEBUG
LOGIC
TX1 SSI
DEBUG
LOGIC
TX2 SSI
LVDS/
CMOS
SSI
INTERFACE
RX1 SSI
TEST
PATTERN GEN
RX2 SSI
TEST
PATTERN GEN
Rev. PrA | Page 58 of 253
Preliminary Technical Data
BASEBAND PROCESSOR
USER Tx DATA
TX1 SSI
TEST
PATTERN GEN
TX2 SSI
USER Tx DATA
USER Rx DATA
TX1 SSI
DEBUG
LOGIC
USER Rx DATA
TX2 SSI
DEBUG
LOGIC