Timing Diagrams - Analog Devices ADRV9001 User Manual

Preliminary Technical Data
• Use the next 32 clock cycles to send the data to be written to the registers, MSB to LSB for each 8-bit word
• Make sure the CSB line is driven high after the last bit has been sent to 0x027 to end the data transfer

TIMING DIAGRAMS

The diagrams in Figure 21 and Figure 22 illustrate the SPI bus waveforms for a single-register write operation and a single-register read
operation, respectively. In the first figure, the value 0x55 is written to register 0x00A. In the second value, register 0x00A is read and the
value returned by the device is 0x55. If the same operations were performed with a 3-wire bus, the SDO line in Figure 21 would be
eliminated, and the SDIO and SDO lines in Figure 22 would be combined on the SDIO line. Note that both operations use MSB-first
mode and all data is latched on the rising edge of the SCLK signal.
CSB
SCLK
SDIO
SDO
WRITE TO REGISTER 0x00A – VALUE = 0x55
CSB
SCLK
SDIO
SDO
READ REGISTER 0x00A – VALUE = 0x55
Table 13 lists the timing specifications for the SPI bus. The relationship between these parameters is shown in Figure 23. This diagram
shows a 3-wire SPI bus timing diagram with the device returning a value of 0xD4 from register 0x00A and timing parameters marked.
Note that this is a single read operation, so the bus-ready parameter after the data is driven from the device (tHZS) is not shown in the
diagram.
Table 13. SPI Bus Timing Constraint Values
Parameter Min
t 20 ns
CP
t 10 ns
MP
t 3 ns
SC
t 0 ns
HC
t 2 ns
S
t 0 ns
H
t 3 ns
CO
t tH
HZM
t 0 ns
HZS
Figure 20. Nominal Timing Diagram, SPI Write Operation
Figure 21. Nominal Timing Diagram, SPI Read Operation
Typical Max Description
SCLK cycle time (clock period)
SCLK pulse width
CSB setup time to first SCLK rising edge
Last SCLK falling edge to CSB hold
SDIO data input setup time to SCLK
SDIO data input hold time to SCLK
8 ns SCLK falling edge to output data delay (3-wire or 4-wire mode)
t (max) Bus turnaround time after baseband processor drives the last address bit
CO
t (max) Bus turnaround time after device drives the last data bit
CO
Rev. PrA | Page 43 of 253
UG-1828