Connection For External Device Clock (Dev_Clk_In) - Analog Devices ADRV9001 User Manual

UG-1828

CONNECTION FOR EXTERNAL DEVICE CLOCK (DEV_CLK_IN)

ADRV9001 can accommodate 3 different types of external clock signals applied at device clock input pins. A differential low voltage
differential signalling (LVDS) clock signal or a single-ended clipped sinewave clock signal from a TCXO can be applied to the device
input pins. Furthermore, a crystal can be connected to device clock input pins to configure it as a crystal oscillator/driver by applying DC
voltage into MODEA pin as shown below;
Table 91. Device Clock Input Interface Modes Description
Voltage Applied at Device Clock Input
MODEA Pin Electrical Interface
0 V (grounded) LVDS
0.45 V CMOS or XTAL
0.9 V CMOS or XTAL
1.35 V CMOS or XTAL
1.8 V CMOS or XTAL
By applying 1.8V to MODEA pin A for CMOS interface mode, a clipped sinewave clock signal from a TCXO can be applied to pin
named DEV_CLK_IN+(E7) via a AC coupling capacitor and pin DEV_CLK_IN-(E8) should be left unconnected.
A Xtal should be connected to both DEV_CLK_IN+ and DEV_CLK_IN- pins with a DC voltage between 0.45 and 1.8V applied to
MODEA pin.
When LVDS mode input clock interface is selected with MODEA pin grounded, an external clock is used as the reference clock for the
RFPLL and the Clocking PLL on the device and thus needs to be a very clean clock source. Connect the external clock inputs to the
DEV_CLK_IN+ (E7) and DEV_CLK_IN- (E8) balls via AC coupling capacitors and should be terminated with 100 Ω as shown in
Figure 185, Figure 186, and Figure 187. The inputs are biased on the device to a 618 mV voltage level. The input impedance plot over
operating frequency is shown on Figure 188. The operational frequency range of the DEV_CLK signal is between 10 MHz and 1000
MHz. Ensure that the external clock peak-to-peak amplitude does not exceed 2V (Note that either positive and negative side of
differential input pins should not exceed 1 Vpeak.). For best synthesizer performance, a high slew rate signal is best with fast rise and fall
times.
0 1 2 3
FREQUENCY (GHz)
Figure 184. External LO1/ External LO2 Insertion Loss, Simulated
DEV_CLK_OUT Divider Value Applied
to DEV_CLK_IN Signal
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Rev. PrA | Page 204 of 253
Preliminary Technical Data
4 5 6
Note
Up to 1GHz clock
CM0S(10MHz to 80MHz)
/XTAL(20 MHz to 80 MHz) with
Nominal Gm multiplier = x8
CM0S(10MHz to 80MHz)
/XTAL(20 MHz to 80 MHz) with
Nominal Gm multiplier = x6
CM0S(10MHz to 80MHz)
/XTAL(20 MHz to 80 MHz) with
Nominal Gm multiplier = x2
CM0S(10MHz to 80MHz)
/XTAL(20 MHz to 80 MHz) with
Nominal Gm multiplier = x4