Ssi Timing Parameters - Analog Devices ADRV9001 User Manual

Preliminary Technical Data
Transmit LSSI Interface with One Lane for I and Q
In this mode, only one lane is used to transfer I and Q data samples. The I/Q data bits can be deserialized with configurable I or Q first
and MSB or LSB first. The STROBE signal can be configured to high for a half clock cycle to indicate the start of I and Q symbols or for
half of I and Q data duration to distinguish when I Data and Q Data.
Figure 49 illustrates the one lane LSSI interface (Tx1 and Tx2) for a 16-bit I/Q data sample with I sample and MSB first configuration.
TX_DCLK_OUT+
TX_DCLK_IN+
OR
TX_DCLK_IN+
TX_STROBE_IN+
OR
TX_STROBE_IN+
TX_IDATA_IN+/–
TX_QDATA_IN+/–

SSI TIMING PARAMETERS

Receive SSI and transmit SSI timing diagram are shown in Figure 50 and Figure 51. The preliminary timing specification for CMOS SSI
is described in Table 16 and the preliminary timing specification for LVDS SSI is described in Table 17.
TX_SROBE/DATA_IN
Table 17. CMOS SSI Timing Specification
CMOS SSI
CMOS Rx t Maximum
DELAY
CMOS Tx t Minimum
SETUP
CMOS Tx t Minimum
HOLD
I0_D15 I0_D14
Figure 49. Transmit LSSI Timing for 16-Bit I/Q Data Sample Sharing One Lane
RX_DCLK_OUT
RX_STROBE/DATA_OUT
Figure 50. Receive SSI Timing Diagram
TX_DCLK_IN
T
SETUP
Figure 51. Transmit SSI Timing Diagram
Timing
5 ns
2 ns
2 ns
I0_D0 Q0_D15 Q0_D14
CLOCK PERIOD
T T
DELAY DELAY
DATA
CLOCK PERIOD
T T T
HOLD SETUP HOLD
DATA DATA
Description
Clock to strobe/data delay
Strobe/data setup to clock
Strobe/data hold after clock
Rev. PrA | Page 57 of 253
I0_Q0 I1_D15
DATA
DATA
UG-1828