Analog Devices ADRV9001 User Manual page 228

UG-1828
ETHERNET
CONNECTION
PC RUNNING TRANSCEIVER
EVALUATION SOFTWARE
Figure 209. ADRV9001 Evaluation Card and ZYNQ ZC706 Evaluation Platform with Connections Required for Testing
The ADRV9001 evaluation system utilizes a Linux operating system. Linux requires time to boot up as well as soft shut down before
hardware power off. The user is expected to use the software power off feature or press the SW9 button on the ZYNQ ZC706 evaluation
platform before physically switching power off using SW1. If this advice is not followed, the file system on the SD card can get corrupted
and the ADRV9001 evaluation system might stop operating.
To set up the evaluation board for testing, follow steps listed below:
1. Connect the ADRV9001 evaluation card and the ZYNQ ZC706 evaluation platform together as shown in Figure 210. Use the LPC
FMC connector (J5). Take care to be sure the connectors are properly aligned.
2. Make sure that all jumpers on the ZYNQ ZC706 evaluation platform as well as the SW11 position (1, 2, 5 = "A" position) match
settings shown in Figure 209.
3. Insert the SD card that came with the ADRV9001 evaluation kit into ZYNQ ZC706 evaluation platform SD card slot (J30).
4. On the ADRV9001 evaluation card, provide a device clock (frequency must match the setting selected in the TES), at a +13dBm
power level to J501 connector. (This signal drives the reference clock into the ADCLK944 clock distribution chip on the board – the
Q1/Q1_N pins of ADCLK944 generates the DEV_CLK for the
platform).
a. It should be noted that quality of clock source used to generate DEV_CLK will directly impact overall system performance.
User needs to ensure that high quality, stable and low phase noise clock source is used here.
5. Connect a 12V, 5A power supply to the ZYNQ evaluation platform at the J22 header.
6. Connect the ZYNQ evaluation platform to the PC with an Ethernet cable (connect to P3). There is no driver installation required.
a. In the case when the Ethernet port is already occupied by another connection, use an USB-to-Ethernet adapter.
b. On an Ethernet connection dedicated to the ZYNQ platform, the user must manually set the following:
i. IPv4 Address to: 192.168.1.2
ii. IPv4 Subnet Mask to: 255.255.255.0
Refer to Figure 211 for more details. The user should make sure that ports listed below are not blocked by firewall software on their PC:
• 22—SSH protocol
• 55557—access to the evaluation software on ZYNQ platform
Note that the ZYNQ ZC706 evaluation platform IP address is set by default to: 192.168.1.10.
POWER
SWITCH
SWITCHING
POWER SUPPLY
(12V DC)
SD CARD FROM
ADRV9001 EVALUATION KIT
Rev. PrA | Page 228 of 253
Preliminary Technical Data
50Ω
TERMINATION
Rx2A
Tx2
EXTERNAL
LO 2
Rx2B
Rx1B
EXTERNAL
LO 1
Tx1 Rx1A
ADRV9002 and REF_CLK for the Xilinx FPGA on the ZYNQ
SIGNAL GENERATOR
J501
SIGNAL GENERATOR
SIGNAL ANALYZER