Digital Front End - Analog Devices ADRV9001 User Manual

System development user guide for the rf agile transceiver family
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Preliminary Technical Data
AFE
Tx1/Tx2
DAC
LPF
Tx1+,
Tx2+
90°
Tx1+,
Tx2–
DAC
LPF
LO
INTERNAL
OBSERVATION
In the DFE subsystem, the SSI interface passes data to the Tx preprocessing blocks including a symbol mapping/interpolation and a 128-
tap programmable FIR filter (PFIR). The symbol mapping/interpolation is used to perform interpolation and/or symbol mapping
necessary for certain NB standards. Please note that if the it is configured as an interpolator, proper filtering of the interpolation images
will be ensured in the PFIR. The PFIR is followed by 2 interpolation stages through a flexible combination of interpolation filters. The
interpolation ratios and filters are controlled by the profiles. By design, the interpolation images are rejected by more than 110dB.
Between the 2 interpolation stages, there is an optional FM/FSK modulator named IQ FM/FSK and a digital upconverter (DUC) which
could both be bypassed. Finally, for IQ data, the signal is interpolated to the DAC sample rate.
As shown in Figure 86, the DFE subsystem also includes various signal conditioning algorithms, such as LO leakage (LOL) suppression
and quadrature error correction (QEC). Besides those, it also provides power amplifier protection and Tx attenuation control blocks.
The output of DFE will first go through the DAC in the AFE subsystem. The DAC standard clock rate can be programmed to be 184.32,
368.64, or 552.96 MHz, which is set by the profile. (Note other sample rates could also be supported when arbitrary sample rate is
employed.) Then, the DAC output is filtered by the LPF and input to the upconversion mixer.
As shown in Figure 86, the ADRV9001 device also supports another method of FM/FSK modulation named Direct FM/FSK modulation.
In this mode, the DUC, IQ FM/FSK, the interpolation stage 2, power amplifier protection and Tx attenuation blocks (digital part) are all
bypassed. RFPLL is utilized to generate a constant envelope phase-modulated signal by modulating the Sigma-Delta Modulator (SDM)
with the data stream. In Direct FM/FSK, both DAC and LPF can be powered down.
In the following subsections, major Tx functionalities will be discussed.

DIGITAL FRONT END

Programmable FIR Filter (PFIR)
The PFIR has 128 taps with 24-bit coefficients. There are 2 FIR filters, which are PFIR_I and PFIR_Q as shown in Figure 87. It can be
configured to operate in parallel, one for I data and one for Q data in digital IQ modulation applications such as LTE. It can also be
configured to use PFIR_I or PFIR_Q only or to operate both filters sequentially for FM/FSK applications. For WB applications, user
could optionally use PFIR as a channel compensation filter, while for NB applications, user could optionally use PFIR as a pulse-shaping
filter. Currently, PFIR is not enabled in the datapath and will be provided to user in the future.
TO NARROWBAND
INTERPOLATOR
Transmit Attenuation Control
Transmit Gain Table
The Tx attenuation block controls the Tx output power. A Tx gain table with 960 entries is loaded into the ADRV9001's memory during
initialization. (Currently only the first 840 entries are used and the remaining 120 entries are reserved for future use.) Each entry equals a
0.05dB gain step. Therefore, there is a total gain range of 42dB. The total Tx attenuation is distributed into two portions, an analog
attenuation portion and a digital attenuation portion. In the analog attenuation, there is a digitally controlled step attenuator (DSA) with
64 unit steps on a linear scale. The gaps between the analog gain steps are interpolated by a 12-bit digital multiplier to 0.05dB steps. The
DFE
INTERPOLATION
DIGITAL
INTERPOLATION
UPCONVERTER
STAGE 2
I/Q
PA
FM/FSK
PROTECTION
FREQUENCY
QUADRATURE
DEVIATION MAPPER
ERROR
FOR DIRECT
CORRECTION
TX
LO MODULATION
ATTENUATION
RF PLL
Figure 86. Tx Datapath Block Diagram
I
PFIR_Q
I,Q
{I,Q}
Figure 87. Programmable FIR Filters
Rev. PrA | Page 91 of 253
INTERPOLATION
STAGE 1
PROGRAMMABLE
128 TAP FIR FILTER
LO LEAKAGE
DIGITAL
SUPPRESSION
PRE-DISTORTION
Q
I
PFIR_I
UG-1828
NCO
2
TX1/2_DCLK_OUT±
SYMBOL
2
MAPPING/
INTERPOLATION
TX1/2_DCLK_IN±
DATA
2
PORT
TX1/2_STROBE_IN±
2
TX1/2_IDATA_IN±
2
TX1/2_QDATA_IN±
LOOPBACK
AFTER TX
PREPROCESSING

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