Lpf; Adc; Digital Front End Components - Analog Devices ADRV9001 User Manual

Preliminary Technical Data UG-1828

LPF

In the Rx data chain, the LPF sits between the mixer and the ADC as a Rx baseband filter, supporting a baseband bandwidth of 5-
50MHz. It also converts the baseband signal current to voltage. The capacitor arrays are implemented to program the various cut-off
frequencies based on the system requirements. In addition, along with other AFE components, it provides a static gain of about 20dB
which is independent of the gain control functionality through the Rx data chain.
The LPF could be configured in transimpedance amplifier (TIA) mode with single pole or in bi-quad (BIQ) mode with 2 complex poles
in the transfer function (Note currently, only TIA mode is supported.). While the in-band performance of both modes is similar, the BIQ
mode offers additional advantages comparing with the TIA mode, such as improving anti-alias filtering which might be necessary while
using LP ADC. However, the use of the BIQ mode consumes about twice the power than the TIA mode.
The LPF is calibrated during device initialization to ensure a consistent frequency corner across all devices. The 3dB bandwidth is set
within the device data structure and is profile dependent.

ADC

As mentioned earlier, the ADRV9001 provides a pair of HP ADCs and a pair of LP ADCs to achieve a flexible trade-off between power
consumption and linearity performance. The HP ADC is based on Continuous Time Delta Sigma (CTDS) architecture and is 5-bits
wide. The LP ADC is based on voltage-controlled oscillator (VCO) architecture and is 16-bits wide. Each type of ADC is capable of
accepting the same input voltage, but the output bus width is different due to the different modulator orders and presence of linearity
correction in the LP ADC.
HP and LP ADCs provide similar level of noise and dynamic range (full scale to thermal noise) performance. Therefore, the noise figure
(NF) performance is similar at the input. (Even with slight NF difference at the device input, the difference at antenna input would be
smaller as a result of the LNA gain in the front end.) The major difference between HP and LP ADC is the linearity performance and
power consumption. The intermodulation distortion (IMD) performance of HP ADC is slightly better than LP ADC, at the expense of
higher power consumption. Please refer to the data sheet for detailed information.
Given the high dynamic range of both the HP and LP ADC, very little channelization or blocker filtering occur in the analog signal chain
since the HP ADC can simultaneously absorb weak signals and large blockers. Blocker suppression and channelization are then achieved
efficiently in the digital signal path.
Therefore, HP ADC provides the maximum interferer tolerance performance and LP ADC provides the best power consumption
performance under slightly relaxed interferer condition. Based on the application, user is allowed to select between HP and LP ADC for
linearity and power consumption performance trade-off. In addition, user is allowed to dynamically switch HP ADC and LP ADC on the
fly through API commands adi_adrv9001_Rx_AdcSwitchEnable_Set( ) and adi_adrv9001_Rx_AdcSwitch_Configure( ). The first API
function is used to enable the ADC switching feature and it should be called at STANDBY state before initial calibrations. When
dynamic ADC switch is enabled, both HP ADC and LP ADC initial calibrations will be performed. The second API configures the ADC
switching functionality for a specified Rx channel to operate in different modes. It should be called at CALIBRATED state after
performing initial calibrations.
When Rx Monitor Mode (not supported currently) is enabled, the device might switch between the HP ADC and LP ADC to reduce
power consumption. Additional algorithms are employed in ADRV9001 to compensate for the gain and delay differences while
operating with different type of ADCs so any internal switch is transparent to users.

DIGITAL FRONT END COMPONENTS

DEC
In Rx data chain, a series of decimators (organized into 2 different decimation stages) are employed to convert the ADC sample rate to a
desired sample rate in both NB and WB modes. The following diagram shows how the standard sampling rates for different standards
are achieved through a flexible combination of decimators in the data chain. For simplicity, any other non-DEC blocks are skipped in the
diagram.
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