Cmos Synchronous Serial Interface (Cmos-Ssi) - Analog Devices ADRV9001 User Manual

Preliminary Technical Data
Table 15. CSSI Electrical Specification
Symbol Parameter
VDIGIO_1P8 Interface power supply voltage
V Input voltage high
IH
V Input voltage low
IL
V Output voltage high
OH
V Output voltage low
OL
f Clock frequency
CLK
C @ 80 MHz Load capacitance supported for
L
an 80 MHz clock waveform
Table 16. LSSI Electrical Specification
Symbol Parameter
VDIGIO_1P8 Interface power supply voltage
V Input voltage range
I
Input Common Mode Voltage
V Input differential threshold
IDTH
R Receiver differential input impedance
IN
V Output voltage high
OH
V Output voltage low
OL
|V | Output differential voltage
OD
V Output offset voltage
OS
R Output impedance, single ended
O
I , I Output current
SA SB
I Output current
SAB
Clock signal duty cycle
T ,T Output Rise/Fall Time
R F

CMOS SYNCHRONOUS SERIAL INTERFACE (CMOS-SSI)

One-Lane Mode CSSI Interface
Receive CSSI Interface
The one-lane mode receive CSSI interfaces of each channel (Rx1 and Rx2) are a 3-wire digital interface consisting of:
RX_DCLK_OUT: is an output clock synchronizing data and strobe output signals.
•
RX_STROBE_OUT: is an output signal indicating the first bit of the serial data sample.
•
RX_DATA_OUT: is an output serial data stream.
•
The I and Q samples are serialized out starting with configurable I or Q first and MSB or LSB first, Figure 25 illustrates the receive CSSI
interface (Rx1 and Rx2) for a 16-bit I/Q data sample with I sample and MSB first configuration.
RX_DCLK_OUT
RX_STROBE_OUT
RX_STROBE_OUT
RX_DATA_OUT
The RX_STROBE_OUT signal is aligned with the first bit of the serialized data (I and Q), and can be configured to be high:
For one clock cycle at start of I and Q sample transmit. In the case a 16-bit data sample, RX_STROBE is high for one clock cycle and low
for 31 clock cycles.
Min
1.71
VDIGIO_1P8 × 0.65
0
VDIGIO_1P8 − 0.45
0
OR
I0_D15 I0_D14
Figure 24. Receive CSSI Timing for 16-Bit I/Q Data Sample (I and MSB First)
Rev. PrA | Page 47 of 253
Typ
1.8
10
Conditions
R = 100 Ω ± 1%
LOAD
R = 100 Ω ± 1%
LOAD
R = 100 Ω ± 1%
LOAD
R = 100 Ω ± 1%
LOAD
Driver shorted to ground
Drivers shorted together
500 MHz
300 mVp swing
I0_D0 Q0_D15 Q0_D14
UG-1828
Max
1.89
VDIGIO_1P8 + 0.18
VDIGIO_1P8 × 0.35
VDIGIO_1P8
0.45
80
30
Min Typ Max
1.71 1.8 1.89
825 1675
925 1200 1575
−100 +100
100
1390
1000
360
1150 1200 1250
80 100 120
17
4.1
45 50 55
0.371
I0_Q0 I1_D15
Units
V
V
V
V
V
MHz
pF
Units
V
mV
mV
mV
Ω
mV
mV
mV
mV
Ω
mA
mA
%
nsec