Analog Devices ADRV9001 User Manual page 122

UG-1828
EXTERNAL FRONT END
GAIN ATTENUATOR
GAIN GAIN
In this gain table, each row provides a unique combination of 6 fields including Front-end Attenuator, TIA Control, ADC Control,
External Gain Control, Phase Offset and Digital Gain/Attenuator. Among them, the TIA Control which sets the TIA gain, the ADC
Control which sets the ADC gain and the Phase Offset which compensates for the phase discontinuity during gain change are reserved
for future use.
Based on the row of this table selected, either by the user in MGC mode, or automatically by the device in AGC mode, the gain control
block updates the variable gain elements depicted by the orange dash lines. In the MGC mode, the user can control the gain control block
using the API commands and DGPIOs.
Table 47 shows the first three and last three rows in a sample gain table.
Table 47. Sample Rows from the Default Rx Gain Table
Gain Table Front-End Attenuator
Index Control Word [7:0]
183 252
184 252
185 251
... ...
253 28
254 14
255 0
The gain table index is the reference for each unique combination of gain settings in the programmable gain table. The possible range of
the gain table is 183 to 255. The gain index region is user configurable. An API function adi_adrv9001_Rx_MinMaxGainIndex_Set()
could be called by the user right after loading the gain table to load multiple gain table regions and switch between multiple gain table
regions during runtime.
Note the External Gain Control which sets the external gain is not supported currently. It is used to control two AGPIO pins for each Rx.
Depending on the hardware register setting, the AGPIO pins for Rx1 and Rx2 can be selected from AGPIO[3:0], AGPIO[7:4] and
AGPIO[11:8]. Table 48 shows an example of Rx1 and Rx2 external gain element control when AGPIO[0:3] is selected (Note it is also
possible to use AGPIO[1:0] for Rx2 and AGPIO[3:2] for Rx1. Please refer to GPIO section in the User Guide for more information.).
Table 48. An Example of Analog GPIOs for External Gain Element Control
Receiver AGPIO Pins to Control External Gain Element
Rx1 AGPIO[1:0]
Rx2 AGPIO[3:2]
These AGPIOs must be enabled as outputs and set for external gain functionality. The 2-bit value programmed is directly related to the
status of these AGPIO pins, for example if the external gain word of the Rx1 gain table is programmed to 3 in selected gain index, then
AGPIO[0] and AGPIO[1] will be high if AGPIO[1:0] is used to control external gain element as the example show in Figure 106.
HB FILTERING
TIA ADC (DECIMATION
STAGE 1)
ANALOG
PEAK HB PEAK
DETECTOR DETECTOR
GAIN CONTROL BLOCK
API
Figure 105. Rx Data Path and Gain Control Blocks
TIA ADC
Control Control
0 0
0 0
0 0
... ...
0 0
0 0
0 0
Rev. PrA | Page 122 of 253
Preliminary Technical Data
WB/NB DECIMATION
(DECIMATION
STAGE 2)
DIGITAL
GAIN CONTROL
POWER RSSI
DETECTOR
(AGC, MGC)
DGPIO(S)
External Gain Phase
Control [1:0] Offset
0 0
0 0
0 0
... ...
0 0
0 0
0 0
INTERFACE
GAIN
(SLICER)
API
Digital Gain/Attenuator
Control Word
[10:0]
25
35
-7
...
-2
-1
0