Analog Devices AD9865 Manual

Broadband modem mixed-signal front end

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FEATURES

Low cost 3.3 V CMOS MxFE

for broadband modems

10-bit D/A converter

2×/4× interpolation filter

200 MSPS DAC update rate

Integrated 23 dBm line driver with 19.5 dB gain control

10-bit, 80 MSPS A/D converter

−12 dB to +48 dB low noise RxPGA (< 3.0 nV/rtHz)

Third order, programmable low-pass filter

Flexible digital data path interface

Half- and full-duplex operation

Backward-compatible with AD9975 and AD9875

Various power-down/reduction modes

Internal clock multiplier (PLL)

2 auxiliary programmable clock outputs

Available in 64-lead chip scale package or bare die

APPLICATIONS

Powerline networking

VDSL and HPNA

GENERAL DESCRIPTION

The AD9865 is a mixed-signal front end (MxFE) IC for

transceiver applications requiring Tx and Rx path functionality

with data rates up to 80 MSPS. Its flexible digital interface,

power saving modes, and high Tx-to-Rx isolation make it well

suited for half- and full-duplex applications. The digital inter-

face is extremely flexible allowing simple interfaces to digital

back ends that support half- or full-duplex data transfers, thus

often allowing the AD9865 to replace discrete ADC and DAC

solutions. Power saving modes include the ability to reduce

power consumption of individual functional blocks, or to power

down unused blocks in half-duplex applications. A serial port

interface (SPI®) allows software programming of the various

functional blocks. An on-chip PLL clock multiplier and

synthesizer provide all the required internal clocks, as well as

two external clocks from a single crystal or clock source.

The Tx signal path consists of a bypassable 2×/4× low-pass

interpolation filter, a 10-bit TxDAC, and a line driver. The

transmit path signal bandwidth can be as high as 34 MHz at an

input data rate of 80 MSPS. The TxDAC provides differential

current outputs that can be steered directly to an external load

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

Broadband Modem Mixed-Signal Front End

PWR DWN

MODE

TXEN/SYNC

TXCLK

ADIO[9:4]/

Tx[5:0]

ADIO[3:0]/

Rx[5:0]

RXE/SYNC

RXCLK

AGC[5:0]

SPI

or to an internal low distortion current amplifier. The current

amplifier (IAMP) can be configured as a current- or voltage-

mode line driver (with two external npn transistors) capable of

delivering in excess of 23 dBm peak signal power. Tx power can

be digitally controlled over a 19.5 dB range in 0.5 dB steps.

The receive path consists of a programmable amplifier

(RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC.

The low noise RxPGA has a programmable gain range of

−12 dB to +48 dB in 1 dB steps. Its input referred noise is less

than 3 nV/rtHz for gain settings beyond 36 dB. The receive path

LPF cutoff frequency can be set over a 15 MHz to 35 MHz

range or simply bypassed. The 10-bit ADC achieves excellent

dynamic performance over a 5 MSPS to 80 MSPS span. Both

the RxPGA and the ADC offer scalable power consumption

allowing power/performance optimization.

The AD9865 provides a highly integrated solution for many

broadband modems. It is available in a space saving 64-pin chip

scale package and is specified over the commercial (−40°C to

+85°C) temperature range.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

FUNCTIONAL BLOCK DIAGRAM

AD9865

2-4X

TxDAC

0 TO –7.5dB

CLK

SYN.

MULTIPLIER

ADC

80MSPS

0 TO 6dB

– 6 TO 18dB

∆ = 1dB

∆ = 6dB

CONTROL

Figure 1.

AD9865

IOUT_G+

IOUT_N+

IAMP

IOUT_N–

IOUT_G–

0 TO –12dB

CLKOUT_1

CLKOUT_2

CLK

OSCIN

XTAL

RX+

2-POLE

1-POLE

LPF

RX–

–6 TO 24dB

∆ = 6dB

www.analog.com

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Summary of Contents for Analog Devices AD9865

Page 1 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use.
Page 2: Table Of Contents
AD9865 TABLE OF CONTENTS Specifications..................3 TxDAC and IAMP Architecture ..........28 Tx Path Specifications..............3 Tx Programmable Gain Control ..........30 Rx Path Specifications..............4 TxDAC Output Operation............30 Power Supply Specifications ............5 IAMP Current-Mode Operation..........30 Digital Specifications ..............6 IAMP Voltage-Mode Operation ..........
Page 3: Specifications
AD9865 SPECIFICATIONS Tx PATH SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; f = 50 MHz, f = 200 MHz, R = 2.0 kΩ, unless otherwise OSCIN noted. Table 1. Parameter...
Page 4: Rx Path Specifications
AD9865 Parameter Temp Test Level Unit Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation) Latency (Relative to 1/ F Full Cycles −0.2 dB Bandwidth Full 0.1095 −3 dB Bandwidth Full 0.1202 Stop Band Rejection (0.289 f to 0.711 f Full OSCIN OSCIN...
Page 5: Power Supply Specifications
AD9865 Parameter Temp Test Level Unit Rx PATH LATENCY Full-Duplex Interface Full 10.5 Cycles Half-Duplex Interface Full 10.0 Cycles Rx PATH COMPOSITE AC PERFORMANCE @ f = 50 MSPS RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p) Signal-to-Noise and Distortion (SNR) 25°C...
Page 6: Digital Specifications
AD9865 Parameter Temp Test Level Unit POWER CONSUMPTION (Half-Duplex Operation with f = 50 MSPS) DATA Tx Mode 25°C AVDD CLKVDD 25°C 49.5 DVDD DRVDD Rx Mode 25°C AVDD CLKVDD 25°C 36.5 DVDD DRVDD POWER CONSUMPTION OF FUNCTIONAL BLOCKS AVDD...
Page 7: Serial Port Timing Specifications
AD9865 SERIAL PORT TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 5. Parameter Temp Test Level Unit WRITE OPERATION (See Figure 46) SCLK Clock Rate (f...
Page 8: Full-Duplex Data Interface (Tx And Rx Port) Timing Specifications
AD9865 FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 7. Parameter Temp Test Level Unit Tx PATH INTERFACE (See Figure 53) Input Nibble Rate (2×...
Page 9: Absolute Maximum Ratings
AD9865 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Rating Stresses above those listed under the Absolute Maximum ELECTRICAL Ratings may cause permanent damage to the device. This is a AVDD, CLKVDD Voltage 3.9 V maximum stress rating only; functional operation of the device at these or DVDD, DRVDD Voltage 3.9 V maximum...
Page 10: Pin Configuration And Function Descriptions
AD9865 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVSS ADIO9/Tx[5] AVSS ADIO8/Tx[4] PIN 1 IOUT_N– ADIO7/Tx[3] IDENTIFIER IOUT_G– ADIO6/Tx[2] AVSS ADIO5/Tx[1] AVDD ADIO4/Tx[0] AD9865 REFIO ADIO3/Rx[5] TOP VIEW REFADJ ADIO2/Rx[4] (Not to Scale) AVDD ADIO1/Rx[3] AVSS ADIO0/Rx[2] NC/Rx[1] RX– NC/Rx[0] AVSS RXEN/RXSYNC...
Page 11 AD9865 Pin No. Mnemonic Mode Description TXCLK ADIO Sample Clock Input TXQUIET Fast TxDAC/IAMP Power-Down RXCLK ADIO Request Clock Input Rx and Tx Clock Output at 2 x f 17, 64 DRVDD Digital Output Driver Supply Input 18, 63 DRVSS...
Page 12: Typical Performance Characteristics
AD9865 TYPICAL PERFORMANCE CHARACTERISTICS Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, f = 50 MSPS, low-pass filter’s f = 22 MHz, AIN = −1 dBFS, OSCIN −3 dB RIN = 50 Ω, half- or full-duplex interface, default power bias settings.
Page 13 AD9865 Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, f = 80 MSPS, low-pass filter’s f = 30 MHz, AIN = −1 dBFS, OSCIN −3 dB RIN = 50 Ω, half- or full-duplex interface, default power bias settings.
Page 14 –0.1 –2 –0.2 DEVICE 1 –3 –0.3 DEVICE 2 AD9865: GAIN STEP ERROR @ +25 ° C DEVICE 3 –4 AD9865: GAIN STEP ERROR @ +85 ° C –0.4 DEVICE 4 AD9865: GAIN STEP ERROR @ –40 ° C –5 –0.5...
Page 15 AD9865 Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, f = 50 MSPS, low-pass filter disabled, RxPGA = 0 dB, AIN = −1 dBFS, OSCIN RIN = 50 Ω, half- or full-duplex interface, default power bias settings.
Page 16: Txdac Path Typical Performance Characteristics
AD9865 TxDAC PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, f = 50 MSPS and 80 MSPS, RSET = 1.96 kΩ, 2:1 transformer coupled output OSCIN (see Figure 63) into 50 Ω load half- or full-duplex interface, default power bias settings.
Page 17 AD9865 –20 –20 PAR = 11.4 PAR = 11.4 RMS = –1.4dBm RMS = –1.4dBm –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 33. Spectral Plot of 84-Carrier OFDM Test Vector Figure 36.
Page 18: Iamp Path Typical Performance Characteristics
AD9865 IAMP PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, f = 50 MSPS, R = 1.58 kΩ, 1:1 transformer coupled output (see Figure 64 and OSCIN Figure 65) into 50 Ω load, half- or full-duplex interface, default power bias settings.
Page 19: Serial Port
AD9865 SERIAL PORT Table 10. SPI Register Mapping Power-Up Default Value Address Break- MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex) (Hex) down Description Width Comments CONFIG = 0 CONFIG = 1 CONFIG = 0 CONFIG = 1 SPI PORT CONFIGURATION AND SOFTWARE RESET...
Page 20 AD9865 Power-Up Default Value MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex) Address Break- (Hex) down Description Width Comments CONFIG = 0 CONFIG = 1 CONFIG = 0 CONFIG = 1 0x08 (7:0) Rx Filter Tuning Refer to Low-Pass Filter...
Page 21: Register Map Description
Tx path and RxPGA gain mapping. SERIAL PORT INTERFACE (SPI) The serial port of the AD9865 has 3- or 4-wire SPI capability The AD9865 serial port can support both MSB (most allowing read/write access to all registers that configure the significant bit) first and LSB (least significant bit) first data device’s internal parameters.
Page 22 SDIO byte that includes the register address of the first address to be Figure 47. SPI 3-Wire Read Operation Timing accessed. The AD9865 automatically increments the address for each successive byte required for the multibyte communication cycle. Figure 48 illustrates the timing for a 4-wire read operation to the SPI port.
Page 23: Digital Interface
The half-duplex interface can be configured to act as a slave or a TXEN master to the digital ASIC. An example of a slave configuration is shown in Figure 51. In this example, the AD9865 accepts all ADIO[9:0] the clock and control signals from the digital ASIC. Because the...
Page 24: Full-Duplex Mode
OSCIN can also be directed to RXCLK by CLKOUT OSCIN setting Bit 2 of Register 0x05. This feature allows the AD9865 to be completely powered down (including the clock synthesizer) while serving as the master. Figure 51. Example of a Half-Duplex Digital Interface...
Page 25: Rxpga Control
RxPGA CONTROL The default Tx and Rx data input formats are twos complement, The AD9865 contains a digital PGA in the Rx path that is used but can be changed to straight binary. The default TXSYNC and to extend the dynamic range. The RxPGA can be programmed RXSYNC settings can be changed such that the first nibble of over −12 dB to +48 dB with 1 dB resolution using a 6-bit word,...
Page 26 AD9865 RXCLK Tx SYNC Tx [5:0] GAIN GAIN Figure 57. Updating RxPGA via Tx[5:0] in Full-Duplex Mode Updating the RxPGA (or TxPGA) via the PGA[5:0] port is an –6 option for both the half-duplex and full-duplex interface. The –12 PGA port consists of an input buffer that passes the 6-bit data...
Page 27: Txpga Control
The TxPGA register can be updated via the PGA[5:0] port or SPI port. The first method should be considered for fast updates The AD9865 also contains a digital PGA in the Tx path distri- of the TxPGA register. Its operation is similar to the description buted between the TxDAC and IAMP.
Page 28: Transmit Path
AD9865 TRANSMIT PATH The AD9865 (or AD9866) transmit path consists of a selectable The pipeline delays of the 2× and 4× filter responses are 21.5 digital 2×/4× interpolation filter, a 10-bit or 12-bit TxDAC, and and 24 clock cycles, respectively, relative to f .
Page 29: Change To Txdac And Iamp Architecture Section
AD9865 clearing Bit 0 of Register 0x0E. As a result, the IOUTP pins Applications demanding the highest spectral performance must remain completely open, if the IAMP is to be used. The and/or lowest power consumption can use the TxDAC output IAMP contains two sets of current mirrors that are used to directly.
Page 30: Tx Programmable Gain Control
AD9865 Table 19. SPI Registers for TxDAC and IAMP Address (Hex) Description 0.1µF 0x0E TxDAC output 0x10 Enable current mirror gain settings (6:4) Secondary path first stage gain of 0 IOUTN+ to 4 with ∆ = 1 IOUTG+ Not used...
Page 31: Iamp Voltage-Mode Operation
AD9865 outputs left open for optimum linearity performance. The IAMP VOLTAGE-MODE OPERATION transformer should be specified to handle the dc standing The voltage-mode configuration is shown in Figure 65. This current, I , drawn by the IAMP. Also, because I...
Page 32: Iamp Current Consumption Considerations
(for example, power lines) in which the Tx output driver must go into a high impedance state while in Rx mode. If the AD9865 is TxDACs AVDD configured for the half-duplex mode (MODE = 0), the IAMP,...
Page 33: Receive Path
RECEIVE PATH does not get amplified with high RxPGA gain settings, The receive path block diagram for the AD9865 (or AD9866) is potentially exceeding the ADC input range. shown in Figure 68. The receive signal path consists of a 3-stage RxPGA, a 3-pole programmable LPF, and a 10-bit (or 12-bit) To limit the RxPGA’s self-induced input offset, an offset...
Page 34: Low-Pass Filter
AD9865 1.30 0.25 LOW-PASS FILTER 1.25 NORMALIZED GAIN RESPONSE The low-pass filter (LPF) provides a third order response with a 1.20 –0.25 cutoff frequency that is typically programmable over a 15 MHz 1.15 –0.50 to 35 MHz span. Figure 68 shows that the first real pole is im- 1.10...
Page 35: Analog-To-Digital Converter (Adc)
Register 0x13, as discussed in the Power Control and Dissipation section. Lastly, the ADC can be completely powered ACTUAL 80MHz AND –40°C down for half-duplex operation, further reducing the AD9865’s ACTUAL 80MHz AND +25°C peak power consumption. ACTUAL 80MHz AND +85°C TARGET-DECIMAL EQUIVALENT Figure 74.
Page 36: Agc Timing Considerations
AD9865 Table 21. SPI Registers for Rx ADC REFT Address (Hex) Description 0x04 Duty cycle restore circuit 0.1µF 10µF ADCs 0.1µF ADC clock from PLL 0x07 ADC low power mode REFB 0.1µF 0x13 (2:0) ADC power bias adjust 1.0V AGC TIMING CONSIDERATIONS...
Page 37: Clock Synthesizer
Note: if the reference frequency appearing at OSCIN is chosen shows the SPI registers pertaining to the clock synthesizer. to be equal to the AD9865’s Tx and Rx path’s word rate, then M CLKOUT1 is a divided version of the VCO output and can be is simply equal to log (F).
Page 38 AD9865 at OSCIN (or RXCLK) can be determined upon power up. Also, Table 22. SPI Registers for CLK Synthesizer this clock has near 50% duty cycle, because it is derived from Address (Hex) Description the VCO. As a result, CLKOUT1 should be selected before...
Page 39: Power Control And Dissipation
Register 0x01 to 0x60 and Register 0x02 to Register 0x05 the bits in Register 0x01 are powered down. When the (or vice versa) such that the AD9865’s Tx and Rx path are never PWRDWN is high, the functional blocks corresponding to the powered on simultaneously.
Page 40: Power Reduction Options
Rx circuitry, set Bit 1 and/or Bit 0 to 0. 4 × INTERPOLATION POWER REDUCTION OPTIONS The power consumption of the AD9865 can be significantly reduced from its default setting by optimizing the power 2 × INTERPOLATION consumption versus performance of the various functional blocks in the Tx and Rx signal path.
Page 41 AD9865 Because the CPGA processes signals in the continuous time domain, its performance vs. bias setting remains mostly independent of the sample rate. Table 25 shows how the typical current consumption seen at AVDD (Pins 35 and 40) varies as a function of Bits (7:5), while the remaining bits are maintained at their default settings of 0.
Page 42: Power Dissipation
A hardware ( RESET pin) or software (Bit 5 of Register 0x00) POWER DISSIPATION reset can be used to place the AD9865 into a known state of operation as determined by the state of the MODE and The power dissipation of the AD9865 can become quite high in CONFIG pins.
Page 43: Analog And Digital Loop-Back Test Modes
RESET low for approximately 10 ms upon power- Digital loop-back can be used to test the full-duplex digital interface of the AD9865. In this test, data appearing on the ANALOG AND DIGITAL LOOP-BACK TEST MODES Tx[5:0] port is routed back to the Rx[5:0] port, thereby The AD9865 features analog and digital loop-back capabilities confirming proper bus operation.
Page 44: Pcb Design Considerations
MxFE. partly achieved by incorporating an exposed die paddle on the The AD9865 has several pins that are used to decouple sensitive bottom surface of the package. However, to take full advantage internal nodes. These pins are REFIO, REFB, and REFT. The...
Page 45 AD9865 occur during undershoot or overshoot caused by ringing. If the form a differential pair and should be routed together as a pair. signal traces cannot be kept shorter than about 1.5 inches, series By keeping the traces adjacent to each other, noise coupled onto the signals appears as common mode and is largely rejected by termination resistors (33 Ω...
Page 46: Evaluation Board
AD9865 EVALUATION BOARD independent monitoring of the ac power line. The evaluation An evaluation board is available for the AD9865 and AD9866. board allows complete optimization of power line reference The digital interface to the evaluation board can be configured designs based around the AD9865 or AD9866.
Page 47: Outline Dimensions
AD9865 OUTLINE DIMENSIONS 0.30 9.00 0.25 0.60 MAX BSC SQ 0.18 PIN 1 0.60 MAX INDICATOR PIN 1 INDICATOR 7.25 8.75 EXPOSED PAD 7.10 SQ* BSC SQ (BOTTOM VIEW) VIEW 6.95 0.45 0.40 0.35 0.25 MIN 7.50 0.80 MAX 1.00 12°...

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