Rf And Data Port Transmission Line Layout - Analog Devices ADRV9001 User Manual

Preliminary Technical Data
the internal AUXDAC outputs. To prevent noise coupling into those signals, the user should route them away from digital region
(above the red dotted line highlighted in Figure 197.
• The AuxADC_N signals can be routed using inner PCB layers. Those signals are intended to sense analog voltage levels such as
temperature sensors. To prevent noise coupling into those signals the user should route them away from digital region (above red
dotted line highlighted in Figure 197).
• MODEA signal is intended to setup operation of DEV_CLK_IN± pins (LVDS differential, CMOS single-ended, XTAL with
different bias voltage). User should follow recommendation outlined in RF Port Interface Information section when controlling this
pin.
• MCS± signals should be treated as differential. If multi-chip synchronization feature is intended to be used in end application, those
signals should be routed with traces matching length of DEV_CLK_IN± traces.
BIAS TO GND OR 1.8V ANALOG
Figure 197. ADRV9001 AuxADC, SPI, Analog GPIO/AuxDAC, MCS±, and Digital GPIO Signal Routing Guidelines

RF AND DATA PORT TRANSMISSION LINE LAYOUT

RF Line Design Summary
The RF line design is a compromise between many variables. Line impedance, line to line coupling, and physical size represent the
parameters subject to compromise. Smallest physical size is in direct opposition to the ZCM of the line, which is directly opposed to the
line EMI performance. In addition, the interface between the RF line width and the device ball pad diameter on the PCB represents a
potential discontinuity. As the RF line width approaches the ball pad diameter, the risk associated with potential interface discontinuity
reduces.
ROUTE AS DIFFERENTIAL PAIR
Rev. PrA | Page 215 of 253
UG-1828
4.99kΩ RESISTOR
ALL DIGITAL GPIO
SIGNALS ROUTED
BELOW THE RED LINE