Microprocessor And System Control - Analog Devices ADRV9001 User Manual

UG-1828

MICROPROCESSOR AND SYSTEM CONTROL

ADRV9001 supports quick configuration from idle states to operation and quick transition between receive and transmit states. Those
transitions are handled by internal blocks called stream processors. Stream processor is a processor within the ADRV9001 device
assigned to perform a series of configuration tasks upon an external request. Upon a request from the user, the stream processor
performs a series of actions defined in the image loaded into the ADRV9001 during initialization process.
The stream processor therefore has streams (series of tasks) for:
Tx1 Enable/Tx1 disable
•
Tx2 Enable/Tx2 disable
•
Rx1 Enable/Rx1 disable
•
Rx2 Enable/Rx2 disable
•
Enabling and disabling paths is done typically using pins, however can also be controlled over the SPI bus using API command. The
stream is not limited to path enabling events and can react to other events such as a DGPIO input signal.
ADRV9001 is flexible in its configuration, and therefore, the stream is flexible. In the same way as the initialization structures change
with profile, so the stream processor image needs to change with configuration, for example, the stream that enables Rx1 differs
depending on whether a narrowband or a wideband setup is chosen. For this reason, it is necessary to utilize a stream image for each
configuration of the device. In this way, when the user saves configuration files (.c) using the ADRV9001 TES, a stream image is also
saved automatically. This stream file should then be used when using these configuration files.
Figure 53 describes the general ecosystem of ADRV9001. On the right-hand side (data side), ADRV9001 interfaces with the BBIC and on
the left hand side (antenna side), it interfaces with the RF components. The following section describes control of the ADRV9001
datapaths.
SWITCH
SWITCH
LNA
LNA
PA
PA
LNA1_CTRL
LNA2_CTRL
RF_SWITCH1
RF_SWITCH2
PA1_BIAS
PA2_BIAS
Figure 53. Data Path Control Signals
Rev. PrA | Page 60 of 253
Rx1 DATA PATH
Rx2 DATA PATH
Tx1 DATA PATH
Tx2 DATA PATH
AuxDAC1
PA
RAMP
CONTROL
AuxDAC1
Preliminary Technical Data
Rx1_ENABLE
Rx1
STREAM
PROC.
Rx2_ENABLE
Rx2
STREAM
PROC.
Tx1_ENABLE
Tx1
STREAM
PROC.
Tx2_ENABLE
Tx2
STREAM
PROC.
SPI SPI INTERFACE
INTERFACE
RAMP1_EN
RAMP2_EN
Rx1 SSI
Rx2 SSI
Tx1 SSI
Tx2 SSI