Adrv9002 Block Diagram - Analog Devices ADRV9001 User Manual

UG-1828
ADRV9002 BLOCK DIAGRAM
Rx1
RX1A+
RX1A–
RX1B+
RX1B–
2
MULTI CHIP
SYNCHRONIZATION
MCS
TX1+
TX1–
Tx1
EXT_LO1+
/n
GENERATOR
EXT_LO1–
DEV_CLK
DEV_CLK+
/XTAL
DEV_CLK–
OSCILLATOR
EXT_LO2+
/n
EXT_LO2–
Tx2
TX2+
TX2–
4
AuxADC,
AuxADCs
AuxDACs,
12
ANALOG GPIOs
AGPIOs
RX2A+
RX2A–
RX2B+
RX2B–
Rx2
HP
ADC
LPF
LP
ADC
0°
90°
LP
ADC
HP
ADC
LPF
DAC
LPF
0°
90°
DAC
LPF
LO1
RF VCO1
SYNTHESIZER
RF VCO2
SYNTHESIZER
LO2
GENERATOR
DAC
LPF
0°
90°
DAC
LPF
HP
ADC
LPF
LP
0° ADC
90°
LP
ADC
HP
ADC
LPF
Figure 2.
DIGITAL SIGNAL PROCESSING:
- NARROW/WIDE BAND DECIMATION
- DC OFFSET CORRECTION (DC)
- QUADRATURE ERROR CORRECTION (QEC)
- NUMERICALLY CONTROLLED OSCILLATOR (NCO)
- PROGRAMMABLE FIR FILTER (PFIR)
- AUTOMATIC GAIN CONTROL (AGC)
- RECEIVER SIGNAL STRENGTH INDICATOR (RSSI)
- OVERLOAD DETECTORS
DIGITAL SIGNAL PROCESSING:
- NARROW/WIDE BAND INTERPOLATION
- LOCAL OSCILLATOR LEAKAGE SUPPRESSION (LOL)
- QUADRATURE ERROR CORRECTION (QEC)
- PROGRAMMABLE FIR FILTER (PFIR)
- POWER AMPLIFIER PROTECTION
- TX ATTENUATION CONTROL
- DIRECT PLL MODULATION
- DIGITAL PRE-DISTORTION (DPD)
AUXILIARY
MICROPROCESSOR
CLOCK
GENERATION
CLOCK
GENERATION
ADVANCED FEATURES
- FREQUENCY HOPPING
- DYNAMIC PROFILE SWITCHING
- MONITOR MODE
DIGITAL SIGNAL PROCESSING:
- NARROW/WIDE BAND INTERPOLATION
- LOCAL OSCILLATOR LEAKAGE SUPPRESSION (LOL)
- QUADRATURE ERROR CORRECTION (QEC)
- PROGRAMMABLE FIR FILTER (PFIR)
- POWER AMPLIFIER PROTECTION
- Tx ATTENUATION CONTROL
- DIRECT PLL MODULATION
- DIGITAL PRE-DISTORTION (DPD)
DIGITAL SIGNAL PROCESSING:
- NARROW/WIDE BAND DECIMATION
- DC OFFSET CORRECTION (DC)
- QUADRATURE ERROR CORRECTION (QEC)
- NUMERICALLY CONTROLLED OSCILLATOR (NCO)
- PROGRAMMABLE FIR FILTER (PFIR)
- AUTOMATIC GAIN CONTROL (AGC)
- RECEIVER SIGNAL STRENGTH INDICATOR (RSSI)
- OVERLOAD DETECTORS
ADRV9002 Block Diagram
Rev. PrA | Page 6 of 253
Preliminary Technical Data
2
RX1_DCLK_OUT±
2
DATA
PORT
RX1_STROBE_OUT±
CMOS-SSI
2
OR
LVDS-SSI
RX1_IDATA_OUT±
2
RX1_QDATA_OUT±
2
TX1_DCLK_OUT±
2
DATA
TX1_DCLK_IN±
PORT
2
CMOS-SSI
OR
TX1_STROBE_IN±
LVDS-SSI
2
TX1_IDATA_IN±
2
TX1_QDATA_IN±
6
CONTROL
CONTROLS
INTERFACE
12
DIGITAL GPIOs
DGPIOs
4
SPI PORT
SPI
4
1.8V ANALOG
2
1.8V DIGITAL
4
POWER
MANAGEMENT 1.3V ANALOG
15/10
1.0V DIGITAL
0/9
1.0V ANALOG
(OPTIONAL)
2
TX2_DCLK_OUT±
2
DATA
TX2_DCLK_IN±
PORT
2
CMOS-SSI
OR
TX2_STROBE_IN±
LVDS-SSI
2
TX2_IDATA_IN±
2
TX2_QDATA_IN±
2
RX2_DCLK_OUT±
2
DATA
PORT
RX2_STROBE_OUT±
CMOS-SSI
2
OR
LVDS-SSI
RX2_IDATA_OUT±
2
RX2_QDATA_OUT±