Analog Devices ADRV9001 User Manual page 214

UG-1828
TRACE WITH FB TO 1.0V ANLG + 1µF CAP
TRACE WITH FB TO 1.3V
TRACE WITH FB TO 1.3V
TRACE WITH FB TO 1.3V
TRACE WITH FB TO 1.3V
TRACE WITH FB TO 1.0V ANLG
TRACE WITH FB TO 1.8V ANLG
TRACE WITH FB TO 1.3V
TRACE WITH FB TO 1.0V ANLG
TRACE WITH FB TO 1.8V Tx2
4.7µF CAPACITOR
4.7µF CAPACITOR
TRACE TO 1.8V DIG
Figure 196. ADRV9001 Power Supply Domains with Connection Guidelines, Some Internal LDOs bypassed, 1.0 V Analog Domain Required
Ceramic 4.7 µF bypass capacitors must be placed at the VRFVCO2_1P0, VRFVCO1_1P0, VRX2LO_1P0, VRX1LO_1P0,
VCLKVCO_1P0, VAUXVCO_1P0, VCONV_1P0 and VDIG_0P9 pins. Place these capacitors as close as possible to the device with the
ground side of the bypass capacitor placed so that ground currents flow away from other power pins and their bypass capacitors if at all
possible.
In scenario, when power supply follows recommendation outlined in Figure 196 (some internal LDOs bypassed, external 1.0V analog
domain in use), 4.7 μF capacitors at VRX2LO_1P0, VRX1LO_1P0 pins are not necessary. 1.0 V domains connected to VRFLO1_1P0 and
VRFLO2_1P0 require 1 μF capacitors.
Signals with Lowest Routing Priority
The following guidelines govern those signals that are the lowest signal routing priority. These can be routed after all critical signal routes
have been completed so they don't interfere with the critical component placement and routing. The signals shown in Figure 197 can be
routed with the lowest priority.
• Connect a 4.99 kΩ resistor to RBIAS pin (C14). This resistor must have a 1% tolerance or better.
• The device has support for JTAG boundary scan, and the MODE pin is used to access the function. Connect the MODE pin (L13) to
ground for normal operation. Refer to the datasheet for JTAG boundary scan information.
• Connect the RESETB pin (K13) to VIOCTRL_1P8 with a 10 kΩ resistor for normal operation. The device can be reset by driving
this pin low.
• When routing digital signals from rows K and below, it is important to route them away from the analog section (rows A through H).
Digital signal routing should not pass above the red dotted line highlighted in Figure 197.
• The AGPIO_N signals can be routed using inner PCB layers. Those signals are intended to control analog blocks such as power
amplifiers or low noise amplifiers. The AGPIO_0 thru AGPIO_3 can also be used as general purpose analog outputs when muxed to
4.7µF CAPACITOR 4.7µF CAPACITOR
Rev. PrA | Page 214 of 253
Preliminary Technical Data
TRACE WITH FB TO 1.0V ANLG + 1µF CAP
TRACE WITH FB TO 1.3V
TRACE WITH FB TO 1.3V
TRACE WITH FB TO 1.3V
TRACE WITH FB TO 1.3V
TRACE WITH FB TO 1.0V ANLG
TRACE WITH FB TO 1.8V ANLG
TRACE WITH FB TO 1.3V
TRACE WITH FB TO 1.0V ANLG
TRACE WITH FB TO 1.8V Tx1
4.7µF CAPACITOR
TRACE WITH FB TO 1.0V ANLG
TRACE TO 1.0V DIG.
HIGH CURRENT
4.7µF CAPACITOR