Hardware Operation - Analog Devices ADRV9001 User Manual

Preliminary Technical Data

HARDWARE OPERATION

Start Up
1. Turn on the evaluation system by switching the ZYNQ ZC706 evaluation platform power switch (SW1) to the on position. If
hardware is connected correctly, two green LEDs (D801 and DS901) on the ADRV9001 evaluation card should be on.
The ZYNQ ZC706 evaluation platform uses a Linux operating system. It takes approximately 30 seconds before the system is ready
for operation and can accept commands from PC software. Boot status can be observed on ZYNQ ZC706 evaluation platform GPIO
LEDs (L, C, R, O). The correct sequence should follow the description below:
2. After SW1 is turned on, all 4 LEDs are ON for approximately 15 seconds. During this time the image is copied from the SD card
into FPGA memory.
3. Next, LEDs should start flashing (moving single ON light) which indicates that the Linux operating system is booting up. That
should take another 15 seconds.
4. When LEDs stop flashing, the system is ready for normal operation and awaits connection with the PC over Ethernet (which should
be established using TES).
Shutdown
When shutdown is executed using the TES, the Linux operating system starts the power-down procedure. It takes a few seconds to finish.
All four LEDs blinking together indicates that the user can safely power off the system using SW1 on the ZYNQ ZC706 evaluation
platform. Power off must be executed using TES software or the user must power down ZYNQ ZC706 evaluation platform using SW9
push button (Figure 208) before the user powers off the evaluation system by switching SW1 to off position.
Correct shutdown should be performed by executing one of these options:
• In the TES, select File and then select Shutdown Zynq Platform.
• On the ZYNQ platform, press the SW9 push button.
After a few seconds, when all four GPIO LEDs on the ZYNQ platform blink together, the user can safely power off the system using SW1
on the ZYNQ platform.
Other Considerations
• The reference clock signal (in range from 10 MHz to 1000MHz, CW tone, +13 dBm maximum) should be connected to J501.
• It should be noted that quality of clock source used to generate DEV_CLK directly impacts overall system performance. User needs
to ensure that high quality, stable and low phase noise clock source is used here.
• For receiver testing on the ADRV9001 evaluation card, use a clean signal generator with low phase noise to provide an input signal
to the selected receiver RF input. Use a shielded RG-58, 50 Ω coaxial cable (1 m or shorter) to connect the signal generator.
• To set the input level near the Rx receiver's full scale, the generator level (for a single tone signal) should be set to approximately -
15 dBm. This level depends on the input frequency and the gain settings through the path.
• Note that there should be no input signal applied to the receiver input when performing an init calibration.
• For transmitter testing, connect a spectrum analyzer to either Tx output on the ADRV9001 evaluation card. Use a shielded RG-58,
50 Ω coaxial cable (1m or shorter) to connect the spectrum analyzer.
Figure 210. IP Settings for Ethernet Port Dedicated for ZYNQ ZC706 Evaluation Platform
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