Analog Front-End Components - Analog Devices ADRV9001 User Manual

UG-1828 Preliminary Technical Data
The ADRV9001 supports 3 standard ADC clocks which are ADC-H clock 2211.84MHz, ADC-M clock 1474.56MHz and ADC-L clock
1105.92MHz for both HP ADC and LP ADC (Note ADC clock could vary with arbitrary sample rate.). In the DFE subsystem, the ADC
output signal at 3 different sample rates will go through 2 decimation stages as shown in Figure 96 to convert to the desired sample rate
by using a flexible combination of decimators. Between the 2 decimation stages, there is an optional DDC which is employed in the
applications which adopts IF reception scheme.
At different decimation stages, several signal conditioning algorithms are performed, which are overload detection for gain control, DC
offset correction (DC) and quadrature error correction (QEC) as shown in Figure 96. The overload detection result is utilized by
automatic gain control (AGC) or manual gain control (MGC) algorithms to properly control both analog and digital gain through a Rx
gain table. The analog gain is applied at the front end attenuator to avoid overload/underload situations. The digital gain is applied at the
gain compensation block in the Rx datapath and it has 2 major functionalities: one is to correct the small step size inaccuracy of the front
end analog gain and the other is to compensate for the front end gain change completely so that it is transparent to users. Different Rx
gain tables are loaded for either correction or compensation based on user's configuration during the device initialization. In
ADRV9001, a sophisticated gain control mechanism (AGC/MGC) is provided, please see Rx Gain Control section for more details. DC
and QEC are used to correct the DC offset and quadrature error so that the signal distortion could be minimized to achieve an optimal
performance before sending data to baseband processor. To achieve best performance for different applications, QEC algorithm is
designed differently for WB and NB applications.
After decimation stage 2, the ADRV9001 provides an option to correct small carrier frequency offset through API commands, followed
by a 128-tap programmable PFIR as a channel selection filter. In the future, API commands will be provided for PFIR for more user
interactions.
After PFIR, besides applying the digital gain as discussed earlier, an interface gain could be optionally applied by utilizing the signal
strength measurement from RSSI. The interface gain is applied through a "Slicer" by properly shifting the signal. When the signal is
large, it could be used to avoid saturate the data port due to a limited bit-width and when the signal is small, it could be used to avoid lose
sensitivity. An API command is provided to user to read the signal strength measurement. The interface gain can be applied
automatically in the device or manually by the user through API commands. This is beneficial when saturation is observed in baseband
processor. Please see Rx Gain Control section for more details.
The RSSI could also be utilized as the signal detector in Rx Monitor Mode. In NB applications, at the end of the datapath, the device
provides an optional capability to discriminate the FSK frequency shift and in addition, detect the DMR sync patterns, which is critical
for Rx Monitor Mode. Note phase offset correction capability is also provided at the end of the Rx datapath to ensure the signal fidelity.
In the future, API command will be provided to allow user interaction. Finally, the output signal is sent through CMOS-SSI/LVDS-SSI
data port to baseband processor for further processing.

ANALOG FRONT-END COMPONENTS

Analog Front Attenuator
The analog front attenuator is a PI resistive network that in conjunction with the passive mixer provides a constant 100 Ohm differential
input impedance. It is controlled by the gain control functionality in the receive datapath to adjust the signal gain to avoid overload the
datapath through overload detectors. When a strong interferer presents, the gain will be decreased and when the interferer disappears,
the gain will be increased so that the desired signal level could be adjusted back to the proper level.
The attenuator has 256 gain settings providing an Rx attenuation range from 0 to 20*log(1/256) = -48dB. Typically, only a subset of this
range will be used. In ADRV9001, the range of the attenuation is from 0 to -36dB with a 0.5dB resolution. The gain of the attenuator is
calculated by the following equation:
The fe_gain_cw[7:0] is a 8 bit control word defined in the Rx gain table. Based on the information from the signal detectors, the gain
control algorithm will find the index of this gain table so that the corresponding gain control word at this index could be used to
calculate the gain at the front end attenuator. Please see Rx Gain Control section for more details.
Mixer
Following the RF attenuator is the passive down converting mixer. It is used to down convert the RF signal to IF or baseband. The
passive mixer uses non-overlapping ¼ duty cycle local oscillator generated by the 4 phase 50% duty cycle LO. The non-overlapping time
is controlled by the duty cycle distortion (DCD) circuit. The DCD is implemented by delaying the rising edge of the 50% duty cycle LO.
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