Connection For Multichip Synchronization (Mcs) Input - Analog Devices ADRV9001 User Manual

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1dB system PN degradation compared to an ideal DEVICE CLOCK. For different DEV_CLK frequencies, the table can be scaled
appropriately. Clock source with phase noise performance outlined in Table 92 (or better) allows ADRV9001 to deliver datasheet
performance. It should be noted that Table 92 provide reference information for ADRV9001 operating with LTE type standards. Each
standard will determine its own DEV_CLK phase noise requirements. As an example, Table 93 provides recommendation for DEV_CLK
when ADRV9001 is intended to operate with LMR type standards. Ideally DEV_CLK phase noise requirement should be derived from
customer specific application and its requirements set for adjacent channel rejection.
In general, using a higher phase noise source can degrade performance delivered by ADRV9001 transceiver.
Table 92. DEV_CLK_IN Phase Noise Requirements for 1dB system PN degradation compared to an ideal DEVICE CLOCK
Narrow PLL Loop Bandwidth (Approximately
50 kHz) (Default, Typically <3 GHz)
Frequency Offset 122.88 MHz
From Carrier (dBc/Hz)
100 Hz −113.02
1000 Hz −125.02
10 KHz −133.02
100 KHz −137.02
1 MHz −133.02
10 MHz −104.02
Table 93. DEV_CLK_IN Phase Noise Requirements for LMR Type Applications
Frequency Offset From Carrier
100 Hz
1000 Hz
10 kHz
100 kHz
10 MHz

CONNECTION FOR MULTICHIP SYNCHRONIZATION (MCS) INPUT

A LVDS type MCS signal applied between MCS+(D7) and MCS-(D8) pins is used to provide time alignment synchronization for the
both RF and datalink systems. Similar to device clock input signal, a clock source with fast rise and fall times should be used as MCS
input signal. PCB traces for routing MCS signals should be implemented following guidelines that are similar to LVDS mode device
clock input trace.
153.6 MHz 245.76 MHz
(dBc/Hz) (dBc/Hz)
−111.08 −107.00
−123.08 −119.00
−131.08 −127.00
−135.08 −131.00
−131.08 −127.00
−102.08 −98.00
PLL Loop Bandwidth Optimized for LMR Type Applications, 38.4 MHz (dBc/Hz)
−106
−151
−151
−151
−151
Rev. PrA | Page 206 of 253
Preliminary Technical Data
Wide PLL Loop Bandwidth (Approximately 300 kHz)
(User Configured, Typically >3 GHz )
122.88 MHz 153.6 MHz
(dBc/Hz) (dBc/Hz)
−114.02 −112.08
−127.02 −125.08
−138.02 −136.08
−146.02 −144.08
−147.02 −145.08
−118.02 −116.08
245.76 MHz
(dBc/Hz)
−108.00
−121.00
−132.00
−140.00
−141.00
−112.00