Analog Devices ADRV9001 User Manual page 71

Preliminary Technical Data
typedef struct adi_adrv9001_ChannelEnablementDelays
{
uint32_t riseToOnDelay;
(Rx) is powered up */
uint32_t riseToAnalogOnDelay;
procedure commences */
uint32_t fallToOffDelay;
(Rx) is powered down */
uint32_t guardDelay;
uint32_t holdDelay;
disabled */
} adi_adrv9001_ChannelEnablementDelays_t
Note guardDelay is reserved for future use and forced to 0 by ADRV9001 for both transmitter and receiver channels. In addition to that,
for the transmitter channel, holdDelay is also reserved for future use and forced to 0. For the receiver channel, fallToOffDelay is also
reserved for future use and forced to 0. API Command adi_adrv9001_Radio_ChannelEnablementDelays_Configure( ) should be called
when the channel is in the standby or calibrated state.
To set all those timing parameters properly, user should have prior knowledge about ADRV9001 timing parameters (ADRV9001
provides to user) as well as helping parameters such as the transmit and receive propagation delay. The prior timing parameters include
enableSetupDelay, propagationDelay, and maximum intended power savings mode, t
Table 23 summarizes all these timing parameters for both transmit and receive. Note all timing parameters specified in units of time
assume a system clock frequency of 184.32 MHz. If using a different system clock frequency, it must be adjusted by
scaleFactor = 184.32 (MHz)/system clock Frequency
Table 23. Prior Tx/Rx Timing Parameters
No PLL Retuning at Frame Boundary
(Use Case in Figure 63)
enableSetupDelay Analog Power-Up*scaleFactor
propagationDelay From user's own measurement
t PLL Tuning + PLL Power-Up *scaleFactor
PowerUpPSM1
t PLL Tuning + LDO Tuning + PLL Power-Up *scaleFactor
PowerUpPSM2
The system clock Freq depends on the profile and user could find the corresponding value under TDD Enablement Delays tab in TES.
In addition to that, TES also displays the timing parameters provided by ADRV9001 to help determine the prior transmit/receive timing
parameters as described in Table 23. Figure 65 shows the picture of TES where those timing parameters and the system clock for the
current user selected profile are located.
Figure 65. ADRV9001 Provided Timing Parameters and the System Clock for the Selected Profile in TES
Based on the information provided in Table 23 or Figure 65, user can further configure the ADRV9001 required timing parameters.
/* Delay from rising edge until antenna switch (Tx) or LNA
/* Delay from rising
/* Delay from falling edge until antenna switch (Tx) or LNA
/* Reserved for future use*/
/* Delay from falling edge until the Tx/Rx interface is
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edge until Tx/Rx analog power up
and t .
PowerUpPSM1 PowerUpPSM2
PLL Retuning at frame boundary
(Use Case in Figure 64)
PLL Tuning + Analog Power-Up *scaleFactor
Same as No PLL tuning case
PLL Power-Up *scaleFactor
LDO Tuning + PLL Power-Up *scaleFactor
UG-1828