Analog Devices ADRV9001 User Manual page 11

Preliminary Technical Data
Functionality Constrains and Limitations
RF Front End For LO generation, ADRV9001 utilize internal VCO that generates square wave type signal. A square wave LO would
produce harmonics. For example:
depending of RF matching used on the RF ports user 2nd LO harmonic can be as high as -50dBc and 3rd harmonic
can be as high as -9 dBc. Therefore the RF filtering on the Rx and Tx path must ensure that signals at the LO harmonic
frequencies (up to 9th in some cases) are not affecting overall system performance.
DPD The DPD functionality is not available when ADRV9001 operates in 2R2T FDD mode.
Calibrations During Rx initialization sequence user needs to ensure that there are no signals present at the Rx input (external LNA
should be disabled) and appropriate termination should be present at LNA output to avoid reflections of Rx
calibration tones. Maximum input signal amplitude should not exceed -82 dBm/MHz for wideband modes, TBD
dBm/MHz for narrowband modes. During Tx initialization sequence user needs to ensure that the power amplifier is
powered down to avoid unwanted emission of transmitter calibration tones at the antenna. No transmitter tracking
calibrations are available when ADRV9001 operates in 2R2T FDD mode.
AGPIOs Analog GPIOs (operating at 1.8V level) can be used as read or write digital levels of in the end user system. AGPIOs can
be utilized to control states of external components or read back digital logic levels from external components.
Digital GPIOs can be used to perform real time monitoring of states of internal ADRV9001 blocks. Digital GPIOs
DGPIOs
operating as inputs can allow user to control Rx gain, Tx attenuation, AGC operation and other elements of ADRV9001
TRx. Depending on the ADRV9001 operation up to 4 GPIOs may be utilized by data port interface.
AuxADC AuxADC can be used to monitor analog voltage (e.g. temperature sensor). Maximum AuxADC input voltage can not
exceed 0.9V.
AuxDAC AuxDAC can be used to: control VCXO responsible for generating ADRV9001 Device clock, control any circuitry that
requires analog control voltage up to 1.8V.
DEV_CLK_OUT ADRV9001 provides divided down version of DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This
output is intended to provide reference clock signal to the digital components in the overall system. This output can
be configured to be active after power up and before ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, ADRV9001 can be initialized using API functions only.
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