Analog Gain Control Api Programming - Analog Devices ADRV9001 User Manual

System development user guide for the rf agile transceiver family
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Preliminary Technical Data
SLOW
5 AGC
LOOP
CLOCK
SETTLING
CYCLE
DELAY
To prevent this happening and maintain a perfectly periodic gain recovery event, gain attacks are prevented from happening towards the
end of gain update counter state as shown in Figure 115. If a gain attack would happen in this period, it is delayed until the start of the
next gain update counter state. This can cause gain attacks to be held off for up to 2× SLS + 5 delay, therefore it is recommended to keep
SLS delay as short as possible to minimize the gain attack delay. Note that it is possible to disable this blocking feature, thus allowing gain
attacks to occur anywhere within the gain update counter state, however the periodicity of the gain recovery event is no longer
guaranteed as gain attacks towards the end of the gain update counter state will cause the gain recovery event to be delayed as shown in
Figure 116.
At the expiry of the gain update counter (or low under range interval in "fast recovery" mode), all measurement blocks are reset and any
peak detector counts will be reset back to zero. When the Rx is enabled, the counter begins. This might mean that its expiry is at an
arbitrary phase to the slot boundaries of the signal. The expiry of the counter can be aligned to the slot boundaries by setting the
parameter enableSyncPulseForGainCounter. While this bit is set, the AGC will monitor a DGPIO pin to find a synchronization pulse.
This pulse will cause the reset of the counter at this point of time, hence if the user supplies a DGPIO pulse time aligned to these slot
boundaries then the expiry of the counter will be aligned to slot boundaries. Any of DGPIO pin 0-15 can be used for this purpose.
For example, considering 100us gain update period and a 184.32 MHz AGC clock, a total of 18,432 AGC clocks will exist in the gain
update period:
Gain Update Period (AGC Clocks) = 184.32 MHz × 100 μs = 18,432
As noted, the full gain update period is the sum of the gainUpdateCounter, the slowLoopSettlingDelay and a number of AGC clock
cycles. If the slowLoopSettlingDelay is set to 4, the gain update counter must be set to 18,423 from the following calculation:
Gain Update Period (AGC Clocks) = gainUpdateCounter + slowLoopSettlingDelay +5
Gain Update Period (AGC Clocks) = 18,423 + 4 + 5 = 18,432
When Rx is enabled, the AGC can be kept inactive for a number of AGC clock cycles by using attackDelay_us. This means the user can
specify one delay for AGC reaction when entering Rx mode, and another for after a gain change occurs (slowLoopSettlingDelay).

ANALOG GAIN CONTROL API PROGRAMMING

As mentioned earlier, the Rx gain control mode could be configured as MGC or AGC mode. In both modes, the API function
adi_adrv9001_Rx_GainControl_Configure() is used to configure the gain control blocks, such as the peak detectors and the power
detector for a specific channel. Those detectors are utilized not only in the AGC mode but also could be utilized in MGC mode to feed
user important information. This API function also configures the DGPIO pins for retrieving the signal detectors information. Note
although signal detectors information is critical for MGC mode, it can also be obtained in AGC mode for observation and debugging
purpose.
The composition of the gain control configuration structure adi_adrv9001_GainControlCfg_t will be discussed in details in the next
section. Once it is configured, the desired gain control mode can be enabled by using adi_adrv9001_Rx_GainControl_Mode_Set()API
function.
If MGC mode is selected, as previously discussed, the gain could be manually controlled through API commands or DGPIO pins. In API
command mode, the user selects a gain index in the gain table through the API function adi_adrv9001_Rx_Gain_Set(). The gain index
selected for a channel can be read back through the API function adi_adrv9001_Rx_Gain_Get().
IMMEDIATE
ATTACK
ATTACK
TYPE 2
GAIN UPDATE COUNTER
Figure 116. Immediate Gain Attack Causing Delayed Gain Recovery
GAIN
YES
GAIN
SLOW
SLOW
5 AGC
LOOP
LOOP
CLOCK
SETTLING
SETTLING
CYCLE
DELAY
DELAY
DELAYED
GAIN
RECOVERY
Rev. PrA | Page 135 of 253
UG-1828
GAIN UPDATE COUNTER
DELAYED
RECOVERY
GAIN

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