Product Highlights; Adrv9002; Bandwidth And Sample Rate Support - Analog Devices ADRV9001 User Manual

Preliminary Technical Data

PRODUCT HIGHLIGHTS

ADRV9002

The ADRV9002 delivers a versatile combination of high performance and low power consumption required by battery powered radio
equipment and can operate in both frequency division duplex (FDD) and time division duplex (TDD) modes. The
from 30 MHz to 6000 MHz covering the VHF, licensed and unlicensed cellular bands, and ISM bands. The IC is capable of supporting
both narrowband and wideband standards up to 40 MHz bandwidth on both receive and transmit.
The transceiver consists of direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and
transmitter sub-system includes DC offset correction, quadrature error correction, and programmable digital filters, eliminating the need
for these functions in the digital baseband. In addition, several auxiliary functions such as an auxiliary ADC, auxiliary DACs, and GPIOs
are integrated to provide additional monitoring and control capability.
The fully integrated phase locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the
transmitter, receiver, and clock sections. Careful design and layout techniques have been implemented to provide the isolation
demanded in high performance Mobile Radio applications.
All VCO and loop filter components are integrated to minimize the external component count. The LOs have flexible configuration
options and include fast lock modes.
The transceiver includes low power sleep and monitor modes to save power, which extends battery life of portable devices while
continuing to monitor communication.
The fully integrated low power digital predistortion (DPD) is supported by ADRV9002. It can linearize wideband signals as well as it has
been optimized for narrowband type signals to enable linearization of high efficiency power amplifiers. In use cases where the integrated
DPD is used, main receivers are used as a power amplifier observation path.
Power supply for ADRV9002
are 1.8V, 1.3V, and 1.0V (in internal LDO bypass mode). 1.3V domain feeds directly some blocks and also internal LDO regulators for
some functions to maximum performance. 1.8V analog domain is used to optimize transmitter and auxiliary converter performance.
The digital processing blocks are supplied by a 1.0V source. In addition, a 1.8 V supply is used to supply all GPIO and interface ports that
connect with the baseband processor
High data rate and low data rate interfaces are supported using configurable CMOS or LVDS Synchronous Serial Interface choice.
The core of the ADRV9002
There is also a control interface that utilizes GPIO lines to provide hardware control to and from the device. These pins can be
configured to provide dedicated sets of functions for different application scenarios.
The block diagram in Figure 2 shows a high level view of the functions in the ADRV9002. Descriptions of each block with setup and
control details are provided in subsequent sections of this document.

BANDWIDTH AND SAMPLE RATE SUPPORT

The ADRV9002 supports the reception and transmission of channels up to 40 MHz bandwidth. Standard sample rates of 24 KHz
(typically for narrowband FM waveforms), 144 KHz and 288 KHz (typically for TETRA signals), and 1.92 MHz, 3.84 MHz, 7.68 MHz,
15.36 MHz, 23.04 MHz, 30.72 MHz, and 61.44 MHz (typically for LTE signals) are available.
In addition, the ADRV9002
cannot be supported due to internal clocking constraints.
Sample rate scaling is accomplished by enabling or disabling decimation or interpolation filters in the digital signal chain.
Data Interfaces
The ADRV9002 supports both CMOS and LVDS electrical interfaces for its data lanes. All data lanes support both electrical interfaces,
but concurrent operation of both interfaces is not supported. Each receive and transmit channel has a dedicated set of lanes for
transferring information.
The CMOS bus speed is limited to 80 MHz. Two operating modes are available for the CMOS-SSI electrical interface. For low sample
rates, a mode in which 32 bits (16 bits of I and Q data each) are serialized over a single lane, with two additional lanes total required for a
clock (SDR or DDR) and a frame synchronization signal, supports a maximum sample rate of 2.5 MHz.
For sample rates above 2.5 MHz, single channel data is serialized over four lanes, with two additional lanes total required for a clock
(SDR or DDR) and a frame synchronization signal, supporting a maximum sample rate of 20 MHz.
is distributed across four or five different voltage supplies – 2 or 3 analog and 2 digital. The analog supplies
is controlled via a standard 3 or 4-wire serial port. All software control is communicated via this interface.
supports an almost continuous range of sample rates between 24 KHz and 61.44 MHz. Some sample rates
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ADRV9002 operates