Analog Devices ADRV9001 User Manual page 234

UG-1828
Initialization
The Initialization tab (see Figure 218 and Figure 219) provides access to the settings that determine device startup configuration. This
page allows the user to:
• Set the device clock.
• Set the device clock frequency.
• Set the divisor value applied to the frequency at DEV_CLK_OUT.
• Enable/disable the DEV_CLK_OUT signal (presently, only enable is available).
• Select the clock PLL type to be either high performance or low power (Note that LP PLL supports only certain sampling rates).
• Select the ARM clock divisor value from 1, 2, and 4. Lower ARM clock rate saves power.
• Configure the LO
• Set PLL Retuning to allow or disallow PLL retuning when switching between Tx and Rx
• When Tx and Rx are using the same LO, but different frequency, when switching between Tx and Rx, PLL needs to be
retuned to lock. If Tx and Rx are using different LOs, there is no need to do PLL retuning.
• Set carrier frequency
• Intermediate frequency is supported for RX. Recommended range from 490KHz to 20MHz.
• Set Rx1/Rx2/Tx1/Tx2 carrier source (internal or external, options vary depending of selected setup).
• If external LO is utilized then
• Set the divisor value
• TES informs the user about the external LO frequency that must be provided to the
LO input.
• If Internal LO is used, user has the option to select Best Phase Noise and Best Power Saving for their application. Note only
Sub-1 G frequencies are supported for Best Phase Noise option.
• Select channel control mode (hardware enable signals or API command).
• Select HIGH, MED, or LOW receiver ADC rate.
Figure 217. Board Configuration Tab
Rev. PrA | Page 234 of 253
Preliminary Technical Data
ADRV9002 transceiver at the External