Adrv9001 Communication With Bbic - Analog Devices ADRV9001 User Manual

Preliminary Technical Data
DEV_CLK
MCS
CLK PLL
SAMPLING
CLKGEN MCS
DIVIDERS SAMPLING
MCS
SAMPLING
MCS
SAMPLING
ANALOG
ADRV900x (2)
MCS
MCS
FIRST MCS
ANALOG
DEVICE CLOCK
DIVIDER
SYNCHRONIZATION

ADRV9001 COMMUNICATION WITH BBIC

ADRV9001 sleeps during MCS. BBIC is responsible to inform ARM before MCS operation and wake it afterwards.
The ARM must wait for MCS signals in the following situations:
During system initialization: the ARM is not yet enabled and no action is required from the firmware.
•
During and/or after initial calibration stage, MCS may be required due to changed datapath configuration: if required, the ARM
•
informs the BBIC what kind of MCS it needs, then sleep automatically and wait for an interrupt from the BBIC.
Any time MCS is repeated: the BBIC must notify the ARM, which then sleeps and waits for interrupt.
•
At these times, sleep the ARM using wait for interrupt (WFI) to ensure it is not doing anything that MCS might interfere with. The ARM
always notifies the BBIC before it sleeps by sending one of the ARM ready for MCS signals.
MCS
DIGITAL
DIGITAL CLOCK MCS
DIGITAL CLOCK
RX LVDS CLOCK MCS
RX LVDS CLOCK
Figure 71. Block Diagram For Multichip Synchronization (MCS)
SECOND MCS THIRD MCS
ANALOG ANALOG
PLL REFERENCE
CLOCK DIVIDER
SYNCHRONIZATION SYNCHRONIZATION
Figure 72. Illustration of MCS Pulse Sequence for MCS Synchronization
DEV_CLK
CLK PLL
CLKGEN
DIVIDERS
ANALOG
FOURTH MCS
ANALOG
PLL STATE
CLKGEN DIVIDER
MACHINE
SYNCHRONIZATION
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MCS_2
MCS GENERATION
MCS_1
CLOCK CHIP
CLK_2
CLK_1 CLOCK GENERATION
MCS
MCS
SAMPLING
MCS
SAMPLING
DIGITAL
MCS
DIGITAL CLOCK MCS
SAMPLING
DIGITAL CLOCK
MCS
RX LVDS CLOCK MCS
SAMPLING
RX LVDS CLOCK
ADRV900x (1)
FIRST MCS SECOND MCS
DIGITAL DIGITAL
DIGITAL CLOCK
DIVIDER INTERFACE
SYNCHRONIZATION SYNCHRONIZATION
UG-1828
RX DATA