Time Division Duplexing (Tdd) - Analog Devices ADRV9001 User Manual

Preliminary Technical Data

TIME DIVISION DUPLEXING (TDD)

ADRV9001 supports automatic TDD operation. User can send and receive TDD framed data by configuring this tab. This of course
depends on how system and setup is selected described in the previous sections. ADRV9001 comes with predefined timing
configurations by default. However user can configure the timing as needed.
In the TDD tab, user can configure the following:
• Frame and Sequences
• User can specify the duration of a frame
• User can select from sequencing of frames
• User can specify the number of frames in a sequence.
• Channel Enable Mode
• Automated TDD state machine, this mode allows GUI to transmit and receive TDD framed data
• Automated TDD state machine should be used for TDD evaluation.
• Manual SPI/PIN mode, these modes transmit and receive data continuously.
• RX/TX enables
• User can enable/disable receiver/transmitter channel
• Tollgate Timing Control
• By default, Autopopulate Tollgate is selected
• Tollgate is a term used to indicate in the FPGA when transmitting (Tx) and capturing (Rx) start and end in time
• User can use custom tollgate timing by selecting Customize Tollgate, however as of v7.0, the user is recommended to choose
the autopopulate option
• Frame timing
• A predefined timing is generated by the GUI based on the profile selected
• User can modify the timing by entering Primary Assert/Deassert, Secondary Assert/Deassert
• Assert/Deassert entries are frame locations, they are not durations, for example if RX1 primary assert is 0 and primary deassert
is 10000 μs, this means within the specified frame the RX1 enable is on from 0 to 10000 μs and off for the rest of the frame.
• In Figure 228, it shows visually what primary/secondary assert/deassert mean. Blue and red indicates TX and RX subframe
data.
PRIMARY DEASSERT TIME
Note: as of v0.7.0, user should use predefined values for TDD configurations, ue of custom values may cause exception.
PRIMARY DEASSERT TIME
PRIMARY ASSERT TIME
SECONDARY ASSERT TIME
Figure 228. TDD Frame Timing Illustration
SECONDARY DEASSERT TIME
SECONDARY DEASSERT TIME
SECONDARY DEASSERT TIME
PRIMARY ASSERT TIME
Rev. PrA | Page 245 of 253
UG-1828