Analog Devices ADRV9001 User Manual page 51

Preliminary Technical Data
RX_DCLK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_DATA_OUT I0_D15 I0_D14
Figure 34. Receive CSSI timing with 8× Data Clock Rate for 16-Bit I/Q Data Sample (MSB First), 224 Cycles
Figure 35, Figure 36, and Figure 37 illustrate the Receive CSSI interface (Rx1 and Rx2) in frequency deviation mode with 16-bit data
symbol with 2×, 4×, and 8× clock rates. The strobe pulse validates the start of the 16bits data symbol, the remaining data bits are ignored.
RX_CLOCK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_DATA_OUT I0_D15 I0_D14
RX_CLOCK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_DATA_OUT I0_D15 I0_D14
RX_CLOCK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_DATA_OUT I0_D15 I0_D14
Four-Lane Mode CSSI Interface
The four-lane mode receive CSSI interface of each channel (Rx1 and Rx2) are a 6-wire digital interface consisting of:
RX_DCLK_OUT: is an output clock synchronous data and strobe output signals.
•
RX_STROBE_OUT: is an output signal indicating the first bit of the serial data sample.
•
RX_IDATA0_OUT: is an output serial data stream of I sample low byte.
•
RX_IDATA1_OUT: is an output serial data stream of I sample high byte.
•
RX_QDATA2_OUT: is an output serial data stream of Q sample low byte.
•
RX_QDATA3_OUT: is an output serial data stream of Q sample high byte.
•
16 CYCLES (I SAMPLE) 16 CYCLES (Q SAMPLE)
I0_D0 Q0_D15 Q0_D14
16 CYCLES (I SAMPLE)
I0_D8 I0_D7 I0_D6
Figure 35. Receive CSSI Timing with 2× Data Clock Rate for 16-Bit Data Symbol (MSB First)
16 CYCLES (I SAMPLE)
I0_D8 I0_D7 I0_D6
Figure 36. CSSI Receive Timing with 4× Data Clock Rate for 16-Bit Data Symbol (MSB First)
16 CYCLES (I SAMPLE)
I0_D8 I0_D7 I0_D6
Figure 37. Receive CSSI Timing with 8× Data Clock Rate for 16-Bit Data Symbol (MSB First)
224 CYCLES (NO SAMPLE)
Q0_D0
16 CYCLES (NO SAMPLE)
I0_D0
48 CYCLES (NO SAMPLE)
I0_D0
112 CYCLES (NO SAMPLE)
I0_D0
Rev. PrA | Page 51 of 253
UG-1828
I1_D15 I0_D14
I1_D15 I0_D14
I1_D15 I0_D14
I1_D15 I0_D14