4.
Memory Map
4.2
Bus Matrix
4.2.1.2
2019-02-06
Single boot mode
Flash ROM
Main RAM
BOOT ROM
SSP
UART
Figure 4-4 Bus Matrix of TMPM3V6/3V4
Cortex M3
System
Data
S0
S1
S2
M0
M1
M2
M3
M4
S0
S1
S2
Page 36
Instruction
M0
M1
DNF
M2
VLTD
M3
POR
OFD
M4
RMC
CG
RTC
WDT
ADC
SIO/UART
I2C/SIO
TMRB
PORT
TMPM3V6/M3V4