Toshiba TX03 Series Manual page 496

32 bit risc microcontroller
Table of Contents

Advertisement

22.
Flash Memory Operation
22.3
How to Reprogram Flash using Single Boot Mode
22.3.7
Transfer Format of Flash memory Chip Erase and Protect Bit Erase
This section shows a transfer format of Flash memory chip erase and protect bit erase commands. Transfer
directions in the table are indicated as follows:
Transfer direction (C→T): Controller to TMPM3V6/M3V4
Transfer direction (C←T): TMPM3V6/M3V4 to Controller
Number of
Transfer
transfer
direction
bytes
1
C→T
2
C←T
3
C→T
4
C←T
5 to 16
C→T
17
C→T
2019-02-06
Transfer data
Serial operation mode and baud rate set-
ting
[UART mode]
0x86
ACK response to serial operation mode
[UART mode]
Normal state: 0x86
Operation command data (0x40)
ACK response to the operation command
Normal state: 0x40
Abnormal state: 0xX1
Communication error: 0xX8
Password data (12-byte)
0x3F81_FFF4 to 0x3F81_FFFF
5th to 16th byte CHECK SUM value
Sends data to determine the serial operation mode. For detail of mode determina-
tion, refer to"22.3.5.1 Serial Operation Mode Determination".
Sends 0x86. If UART mode is determined, checks if baud rate setting can be
done. If not, operation stops communications.
The 2nd byte of transmit data is a ACK response data to the 1st byte that corre-
sponds to the serial operation setting mode data. If the setting is possible, sets SIO/
UART. A receive enable timing is set before transmit buffer is written to the data.
If the setting is determined to be possible, sends 0x86. If not, the operation aborts
without sending back any response.
When the controller finished to send the 1st byte of data, requires a time-out time
(5 seconds). If data (0x86) is not normally received within a time-out time, communi-
cation is not possible.
Sends Flash memory chip erase and protect bit erase command data (0x40).
ACK response data to the operation command.
First, checks if 3rd byte of receive data has errors. (UART mode only) If receive er-
rors exist, sends a ACK response data 0xX8 that means abnormal communica-
tions and waits for a next operation command (3rd byte). Upper 4 bits of transmit da-
ta are undefined. (same as upper 4 bits of immediately before operation command
data.) Note that in the I/O interface, receive error check is not performed.
Then, if the 3rd byte of receive data corresponds to either operation command da-
ta in Table 22-12, receive data is echoed back. If the data does not correspond to
the command in Table 22-12, sends a ACK response data 0xX1 that means opera-
tion command errors, and waits for next operation command. (3rd byte) Upper 4
bits of transmit data are undefined. (Upper 4 bits of immediate before operation com-
mand data are used.)
If password necessity is set to "none", this data is dummy data.
If password necessity is set to "necessary", checks data in the password area. For
a method of password area data checking, refer to "22.3.5.3 Password Determina-
tion".
Compares 5th to 16th byte of receive data with 0x3F81_FFF0 to 0x3F81_FFFF of
data of Flash memory in order. If the data does not match, a password error flag
is set.
Sends 5th byte to 16 byte of CHECK SUM value.
For a method of CHECK SUM calculation, refer to"22.3.5.4 CHECK SUM Calcula-
tion".
Page 474
TMPM3V6/M3V4
Description

Advertisement

Table of Contents
loading

This manual is also suitable for:

Tmpm3v6Tmpm3v4

Table of Contents