Toshiba TX03 Series Manual page 100

32 bit risc microcontroller
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7.
Exceptions
7.1
Overview
(3)
Note:
<PRI_n> bit is defined as a 3-bit configuration with this product.
Table 7-2 Priority grouping setting
7.1.2.2
rupt service routine. This is called "pre-emption".
2019-02-06
Priority setting
・ Priority levels
The external interrupt priority is set to the interrupt priority register and other exceptions
are set to <PRI_n> bit in the system handler priority register.
The configuration <PRI_n> can be changed, and the number of bits required for setting
the priority varies from 3 bits to 8 bits depending on products. Thus, the range of priority val-
ues you can specify is different depending on products.
In the case of 8-bit configuration, the priority can be configured in the range from 0 to
255. The highest priority is "0". If multiple elements with the same priority exist, the small-
er the number, the higher the priority becomes.
・ Priority grouping
The priority group can be split into groups. By setting the <PRIGROUP> of the applica-
tion interrupt and reset control register, <PRI_n> can be divided into the pre-emption prior-
ity and the sub priority.
A priority is compared with the pre-emption priority. If the priority is the same as the pre-
emption priority, then it is compared with the sub priority. If the sub priority is the same
as the priority, the smaller the exception number, the higher the priority.
The Table 7-2 shows the priority group setting. The pre-emption priority and the sub pri-
ority in the table are the number in the case that <PRI_n> is defined as an 8-bit configuration.
<PRI_n[7:0]>
<PRIGROUP[2:0]>
Pre-emption
setting
field
000
[7:1]
001
[7:2]
010
[7:3]
011
[7:4]
100
[7:5]
101
[7:6]
110
[7]
111
None
Note: If the configuration of <PRI_n> is less than 8 bits, the lower bit is "0". For the exam-
ple, in the case of 3-bit configuration, the priority is set as <PRI_n[7:5]> and <PRI_n[4:0]
> is "00000".
Exception Handling and Branch to the Interrupt Service Routine (Pre-emption)
When an exception occurs, the CPU suspends the currently executing process and branches to the inter-
Number of
pre-emption
Subpriority
priorities
field
[0]
128
[1:0]
64
[2:0]
32
[3:0]
16
[4:0]
8
[5:0]
4
[6:0]
2
[7:0]
1
Page 78
TMPM3V6/M3V4
Number of
subpriorities
2
4
8
16
32
64
128
256

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