Toshiba TX03 Series Manual page 271

12.10.3.5 Under-run error
In the I/O interface mode with clock input mode and if FIFO is empty and if no data is set in transmit buf-
fer before the next frame clock input, which occurs upon completion of data transmission from transmit
shift register, an under-run error occurs and SCxCR<PERR> is set to "1".
The level of a TXDx pin can be specified by SCxCR<TXDEMP>. When SCxCR<TXDEMP> is "0", a
TXDx pin outputs "Low" level during data output period. When SCxCR<TXDEMP> is "1", a TXDx pin out-
puts "High" level.
SCLKx input
TXDx pin
(SCxCR<TIDLE[1:0]>="00"
SCxCR<TXDEMP="0"))
TXDx pin
(SCxCR<TIDLE[1:0]>="00"
SCxCR<TXDEMP="1"))
TXDx pin
(SCxCR<TIDLE[1:0]>="01"
SCxCR<TXDEMP="0"))
TXDx pin
(SCxCR<TIDLE[1:0]>="01"
SCxCR<TXDEMP="1"))
TXDx pin
(SCxCR<TIDLE[1:0]>="10"
SCxCR<TXDEMP="0"))
TXDx pin
(SCxCR<TIDLE[1:0]>="10"
SCxCR<TXDEMP="1"))
Figure 12-10 Level of TXDx pin when Under-run Error is Occurred
In the I/O interface mode with SCLK output setting, the clock output automatically stops, so
SCxCR<PERR> has no meaning.
Note: Before switching the I/O interface mode with clock output mode to other modes, read the SCxCR
and clear the under-run flag.
12.10.3.6 Data Hold Time In the I/O interface mode with clock input mode
In the I/O interface mode with clock input mode, a data hold time of the last bit can be adjusted by
SCxCR<EHOLD[2:0]>. Specify a data hold time and the period of the SCLK to satisfy the following for-
mula.
The data hold time of the last bit ≤ The period of SCLK / 2
Under-run error
Low
Low
High
High
Keep the last bit
Keep the last bit
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TMPM3V6/M3V4
Low Low
High Low
Low High
High High
Low Low
High High
2019-02-06