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20.
Oscillation Frequency Detector (OFD)
20.3
Operational Description
20.3
Operational Description
20.3.1
Setting
All register except OFDCR1 can not be written by reset. They are can be written by writing "0xF9" to
OFDCR1.
To protect the mistaken writing, should be written "0x06" to OFDCR1 after setting all registers. And the reg-
ister should be modified when OFD is stopped.
20.3.2
Operation
From the operation start-up to detection start-up, time length as two cycle of detecting clock is needed.
OFDSTAT<OFDBUSY> can confirm whether it is operating. Detecting cycle is (reference clock frequen-
cy) / 2
When generating reset is enabled, the reset is generated if the following condition is satisfied.
・ When a target clock frequency is over than the range of a frequency which is specified by
・ When the reference clock stops.
When generating reset is disabled, OFDSTAT<FRQERR> can be confirmed the condition
Note: There are several factors of reset. Clock generator register CGRSTFLG can confirm the factors. For de-
2019-02-06
MHz.
8
OFDMX and OFDMN.
tails of CGRSTFLG see chapter "exception."
Page 428
TMPM3V6/M3V4
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