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10.
16-bit Timer / Event Counters (TMRB)
10.4
Registers
10.4.7
TBxST (Status register)
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
Bit Symbol
31-3
−
2
INTTBOF
1
INTTB1
0
INTTB0
Note 1: The factors only which is not masked by TBxIM output interrupt request to the CPU. Even if the mask setting is
Note 2: The flag is cleared by reading the TBxST register.To clear the flag, TBxST register should be read.
2019-02-06
31
30
29
-
-
-
0
0
0
23
22
21
-
-
-
0
0
0
15
14
13
-
-
-
0
0
0
7
6
5
-
-
-
0
0
0
Type
R
Read as "0".
R
Overflow flag
0:No overflow occurs
1:Overflow occurs
When an up-counter is overflow, "1" is set.
R
Match flag (TBxRG1)
0:No detection of a match
1:Detects a match with TBxRG1
When a match with the timer register 1 (TBxRG1) is detected, "1" is set.
R
Match flag (TBxRG0)
0:No match is detected
1:Detects a match with TBxRG0
When a match with the timer register 0 (TBxRG0) is detected, "1" is set.
done, the flag is set.
28
27
-
-
0
0
20
19
-
-
0
0
12
11
-
-
0
0
4
3
-
-
INTTBOF
0
0
Function
Page 166
TMPM3V6/M3V4
26
25
24
-
-
-
0
0
0
18
17
16
-
-
-
0
0
0
10
9
8
-
-
-
0
0
0
2
1
0
INTTB1
INTTB0
0
0
0
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