Toshiba TX03 Series Manual page 299

13.4.4 SBISR (Status Register)
This register serves as SBICR2 by writing to it.
31
bit symbol -
After reset 0
23
bit symbol -
After reset 0
15
bit symbol -
After reset 0
7
bit symbol MST
After reset 0
Bit Bit Symbol Type
31-8 - R
7 MST R
6 TRX R
5 BB R
4 PIN R
3 AL R
2 AAS R
1 ADO R
0 LRB R
30 29 28
- - -
0 0 0
22 21 20
- - -
0 0 0
14 13 12
- - -
0 0 0
6 5 4
TRX BB PIN
0 0 1
Read as 0.
Master/slave selection monitor
0: Slave mode
1: Master mode
Transmit/receive selection monitor
0: Receive
1: Transmit
I2C bus state monitor
0: Free
1: Busy
INTSBI interrupt request monitor
0:Interrupt request generated
1: Interrupt request cleared
Arbitration lost detection
0: −
1:Detected
Slave address match detection
0: −
1: Detected
(This bit is set when the general-call address is detected as well.)
General call detection
0: −
1:Detected
Last received bit monitor
0:Last received bit "0"
1:Last received bit "1"
Page 277
27 26 25
- - -
0 0 0
19 18 17
- - -
0 0 0
11 10 9
- - -
0 0 0
3 2 1
AL AAS ADO
0 0 0
Function
TMPM3V6/M3V4
24
-
0
16
-
0
8
-
0
0
LRB
0
2019-02-06