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9.
Input / Output port
9.1
Registers
9.1.2.11
Table 9-11 PORT L Setting List
Reset status
PO
RT
PL0
After reset
Input Port
Output Port
PL2
After reset
Input Port
Output Port
INTF
Note 2: PL0 works as a BOOT function. It is enabled to be input and pulled-up while RESET pin is "Low". At the rising edge
of the reset signal, if PL0 is "High", the device enters single chip mode and boots from the on-chip flash memory. If
PL0 is "Low", the device enters single BOOT mode and boots from the internal BOOT program.
2019-02-06
PORT L
PORT
Input/Output
Type
Input
Output
Input
Output
Input
FT4
Control registers
PLDATA
PLCR
PLFRn
0
0
0
0/1
0
0
0/1
1
0
0
0
0
0/1
0
0
0/1
1
0
0/1
0
PLFR1
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TMPM3V6/M3V4
PLOD
PLPUP
PLPDN
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PLIE
0
1
0 (Note1)
0
1
0
1
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