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13.
Serial Bus Interface (I2C/SIO)
13.6
Data Transfer Procedure in the I2C Bus Mode
Settings in main routine
Reg.
Reg.
if Reg.
Then
SBICR1
SBIDBR
SBICR2
13.6.2.2
tion bit from the master device during the first eight clocks on the SCL line.
dress, the SBI pulls the SDA line to the "Low" level during the ninth clock and outputs an acknowledg-
ment signal.
"0". In the slave mode, the SBI holds the SCL line at the "Low" level while <PIN> is "0".
SCL pin
SDA pin
<PIN>
INTSBIinterrupt
request
Figure 13-9 Generation of the Start Condition and a Slave Address
2019-02-06
7
6
5
4
←
SBISR
←
Reg. e 0x20
≠
0x00
←
X
X
X
1
←
X
X
X
X
←
1
1
1
1
Example of INTSBI0 interrupt routine
Clears the interrupt request.
Processing
End of interrupt
Slave mode
In the slave mode, the SBI receives the start condition and a slave address.
After receiving the start condition from the master device, the SBI receives a slave address and a direc-
If the received address matches its slave address specified at SBII2CAR or is equal to the general-call ad-
The INTSBI interrupt request is generated on the falling of the ninth clock, and <PIN> is cleared to
1
2
A6
A5
Start condition
3
2
1
0
Ensures that the bus is free.
0
X
X
X
Selects the acknowledgement mode.
X
X
X
X
Specifies the desired slave address and direction.
1
0
0
0
Generates the start condition.
3
4
5
A4
A3
A2
A1
Slave address + Direction bit
Page 288
6
7
8
9
A0
R/W
ACK
Master output
Slave output
TMPM3V6/M3V4
Acknowledgement from
slave device
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