Toshiba TX03 Series Manual page 255

12.6 Clock Control
12.6.1 Prescaler
There is a 7-bit prescaler to divide a prescaler input clock φT0 by 1, 2, 4, 8, 16, 32, 64 and 128.
Use the CGSYSCR and SCxEN<BRCKSEL> in the clock/mode control block to select the input clock of
the prescaler.
The prescaler becomes active only when the baud rate generator is selected as a transfer clock by
SCxMOD0<SC[1:0]> = "01".
12.6.2 Serial Clock Generation Circuit
The serial clock generation circuit is a block to generate transmit and receive clocks (SIOCLK) and con-
sists of the circuits in which clocks can be selected by the settings of the baud rates generator and modes.
12.6.2.1 Baud Rate Generator
The baud rate generator generates transmit and receive clocks to determine the serial channel transfer
rate.
(1) Baud Rate Generator input clock
The input clock of the baud rate generator is selected from the prescaler outputs divided by 1, 4,
16 and 64.
This input clock is selected by setting the SCxEN<BRCKSEL> and SCxBRCR<BRCK>.
(2) Baud Rate Generator output clock
The frequency division ratio of the output clock in the baud rate generator is set by SCxBRCR
and SCxBRADD.
The following frequency divide ratios can be used; 1/N frequency division in the I/O interface
mode, either 1/N or 1/(N + (16-K)/16) in the UART mode.
The table below shows the frequency division ratio which can be selected.
SCxEN<BRCKSEL> SCxBRCR<BRCK>
0
0
0
0
1
1
1
1
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Baud rate generator
input clock φTx
00 φT0/2
01 φT0/8
10 φT0/32
11 φT0/128
00 φT0
01 φT0/4
10 φT0/16
11 φT0/64
TMPM3V6/M3V4
2019-02-06