Wait Mode - Toshiba TC9314F Manual

2. Wait Mode

Wait mode halts the system and maintains, with reduced current consumption, the internal state of the
system immediately prior to halting. Two wait modes are available: "soft wait" and "hard wait". When the
WAIT instruction is executed, execution halts at the address of the WAIT instruction. Therefore, when wait
mode is released, execution starts again from the next instruction without delaying for the standby time.
(1) Soft wait mode
Executing the WAIT instruction with the operand [P
this mode, the crystal oscillator, display circuit, and other circuitry continue to operate normally.
Using soft wait mode in the program for clock functions reduces the current consumed during clock
operation.
Note 21: The current consumption depends on the program.
(2) Hard wait mode
Executing the WAIT instruction with the operand [P
crystal oscillator. This reduces current consumption still further than soft wait mode. In this state,
the CPU and display circuits are halted, and the LCD display output pins are all automatically fixed
at the low level. (10 A typ. at V
(3) Setting wait mode
Executing the WAIT instruction always sets wait mode.
Note 22: In hard wait mode, the PLL turns off, while in soft wait mode, the PLL does not turn off.
Accordingly, before setting a soft wait, turn the PLL off by software.
(4) Wait mode release conditions
Wait mode is released by the following conditions.
At a change in the input state of the HOLD pin
1)
2) When a high level is input to a key input pin (K0~K3)
(Note 23: depends on the key input mode)
3) When the 2 Hz timer flip-flop is set to "1". (in soft wait mode only)
4) At a change in the input state of an I/O port (P1-0~P1-3) set as an input port
3. HOLD Input Port
The HOLD pin can be used as an input port. Executing the IN1 instruction with the operand [C
reads the data input from this bit to data memory.
When setting clock stop mode, always access this port prior to executing the CKSTP instruction. Note
that if the CKSTP instruction is executed without first accessing this port, the device may not enter clock
stop mode.
5 V)
DD
21
0H] stops only the CPU inside the device. In
1H] stops all operation other than the
TC9314F
8H]
N
2003-07-03