Toshiba TX03 Series Manual page 102

7. Exceptions
7.1 Overview
(3)
(4)
7.1.2.3
user.
cur again upon return to normal program execution.
the currently executing ISR and services the newly detected exception.
2019-02-06
Late-arriving
If the CPU detects a higher priority exception before executing the ISR for a previous exception,
the CPU handles the higher priority exception first. This is called "late-arriving".
A late-arriving exception causes the CPU to fetch a new vector address for branching to the corre-
sponding ISR, but the CPU does not newly push the register contents to the stack.
Vector table
The vector table is configured as shown below.
You must always set the first four words (stack top address, reset ISR address, NMI ISR address,
and Hard Fault ISR address).Set ISR addresses for other exceptions if necessary.
Offset Exception
0x00 Reset
0x04 Reset
0x08 Non-Maskable Interrupt
0x0C Hard Fault
0x10 Memory Management
0x14 Bus Fault
0x18 Usage Fault
0x1C to 0x28 Reserved
0x2C SVCall
0x30 Debug Monitor
0x34 Reserved
0x38 PendSV
0x3C SysTick
0x40 External Interrupt
Executing an ISR
An ISR performs necessary processing for the corresponding exception. ISRs must be prepared by the
An ISR may need to include code for clearing the interrupt request so that the same interrupt will not oc-
For details about interrupt handling, see "7.5 Interrupts".
If a higher priority exception occurs during ISR execution for the current exception, the CPU abandons
Contents
Initial value of the main stack
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
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TMPM3V6/M3V4
Setting
Required
Required
Required
Required
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional