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12.
Serial Channel with 4bytes FIFO (SIO/UART)
12.5
Data Format
12.5.2
Parity Control
The parity bit can be added with a transmitted data only in the 7- or 8-bit UART mode. And the received par-
ity bit can be compared with a generated one.
Setting "1" to SCxCR<PE> enables the parity. SCxCR<EVEN> selects either even or odd parity.
12.5.2.1
transmit buffer. The parity bit will be stored in SCxBUF<TB[7]> in the 7-bit UART mode and
SCxMOD0<TB8> in the 8-bit UART mode.
12.5.2.2
in the 8-bit UART mode, it is compared with the one in SCxCR<RB8>.
12.5.3
STOP Bit Length
The length of the STOP bit in the UART transmission mode can be selected from one bit or two bits by set-
ting the SCxMOD2<SBLEN>. The length of the STOP bit data is determined as one-bit when it is received re-
gardless of the setting of this bit.
2019-02-06
Transmission
Upon data transmission, the parity control circuit automatically generates the parity with the data in the
The <PE> and <EVEN> settings must be completed before data is written to the transmit buffer.
Reception
If the received data is moved from the receive shift register to the receive buffer, a parity is generated.
In the 7-bit UART mode, the generated parity is compared with the parity stored in SCxBUF<RB[7]>,
If there is any difference, a parity error occurs and the SCxCR<PERR> is set to "1".
In use of the FIFO, <PERR> indicates that a parity error was generated in one of the received data.
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TMPM3V6/M3V4
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