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7.
Exceptions
7.2
Reset Exceptions
7.2
Reset Exceptions
Reset exceptions are generated from the following five sources.
Use the Reset Flag (CGRSTFLG) Register of the Clock Generator to identify the source of a reset.
・ External reset pin
・ Reset exception by WDT
・ Reset exception by SYSRESETREQ
set Control Register.
・ Reset exception by POR
・ Reset exception by OFD
on the OFD.
・ Reset exception by VLTD
VLTD.
7.3
Non-Maskable Interrupts (NMI)
Non-maskable interrupts are generated from the following two sources.
Use the NMI Flag (CGNMIFLG) Register of the clock generator to identify the source of a non-maskable interrupt.
・ Non-maskable interrupt by WDT
ter on the WDT.
2019-02-06
A reset exception occurs when an external reset pin changes from "Low" to "High".
The watchdog timer (WDT) has a reset generating feature. For details, see the chapter on the WDT.
A reset can be generated by setting the SYSRESETREQ bit in the NVIC's Application Interrupt and Re-
A reset exception occurs when the power is turned on. For details, see the chapter on the POR.
The oscillation frequency detection (OFD) has a reset generating feature. For details, see the chapter
The Voltage Level Detector (VLTD) has a reset generating feature. For details, see the chapter on the
The watchdog timer (WDT) has a non-maskable interrupt generating feature. For details, see the chap-
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TMPM3V6/M3V4
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