Toshiba TX03 Series Manual page 339

14.3.7 SSPIMSC (Interrupt enable/disable register)
31
bit symbol -
After Reset Undefined Undefined
23
bit symbol -
After Reset Undefined Undefined
15
bit symbol -
After Reset Undefined Undefined
7
bit symbol -
After Reset Undefined Undefined
Bit Bit Symbol Type
31-4 − W
3 TXIM R/W
2 RXIM R/W
1 RTIM R/W
0 RORIM R/W
30 29 28
- - -
Undefined Undefined
22 21 20
- - -
Undefined Undefined
14 13 12
- - -
Undefined Undefined
6 5 4
- - -
Undefined Undefined
Write as "0".
Transmit FIFO interrupt enable:
0: Disable
1: Enable
Enable or disable a conditional interrupt to occur if the transmit FIFO is half empty or less.
Receive FIFO interrupt enable:
0: Disable
1: Enable
Enable or disable a conditional interrupt to occur if the receive FIFO is half full or less.
Receive time-out interrupt enable:
0: Disable
1: Enable
Enable or disable a conditional interrupt to indicate that data exists in the receive FIFO to the time-out peri-
od and data is not read.
Receive overrun interrupt enable:
0: Disable
1: Enable
Enable or disable a conditional interrupt to indicate that data was written when the receive FIFO was in
the full condition.
Page 317
27 26
- -
Undefined Undefined Undefined
19 18
- -
Undefined Undefined Undefined
11 10
- -
Undefined Undefined Undefined
3 2
TXIM RXIM RTIM
0 0
Function
TMPM3V6/M3V4
25 24
- -
Undefined
17 16
- -
Undefined
9 8
- -
Undefined
1 0
RORIM
0 0
2019-02-06