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16.4
Register Descriptions
AD conversion is performed at the clock frequency selected in the ADC Clock Setting Register.
16.4.1
ADCLK (Clock Setting Register)
31
bit symbol
-
After reset
0
23
bit symbol
-
After reset
0
15
bit symbol
-
After reset
0
7
bit symbol
-
After reset
0
Bit
Bit Symbol
Type
31-7
−
R
6-3
TSH[3:0]
R/W
2-0
ADCLK[2:0]
R/W
Note: The AD conversion times are 1T = 74×(1/SCLK) in the 12-bit mode and T = 68×(1/SCLK) in the 10-
bit mode.
30
29
28
-
-
-
0
0
0
22
21
20
-
-
-
0
0
0
14
13
12
-
-
-
0
0
0
6
5
4
TSH
1
0
1
Read as "0".
Write as "1001".
AD prescaler output (SCLK) select
000: fc (Note)
001 to 111: Reserved
Page 359
27
26
25
-
-
-
0
0
0
19
18
17
-
-
-
0
0
0
11
10
9
-
-
-
0
0
0
3
2
1
ADCLK
1
0
0
Function
TMPM3V6/M3V4
24
-
0
16
-
0
8
-
0
0
0
2019-02-06
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